diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2017-02-17 17:26:04 -0800 |
|---|---|---|
| committer | Duncan Laurie <dlaurie@chromium.org> | 2017-02-20 04:29:35 +0100 |
| commit | c86fa6d97584ce941d847c1eabf388a226ba2638 (patch) | |
| tree | f4d42097a3f2d3d823caac39db6eb1a49ae87520 /src/mainboard | |
| parent | 6c8238521eaf2216c9a41502be1cb2703a0d6f3e (diff) | |
| download | coreboot-c86fa6d97584ce941d847c1eabf388a226ba2638.tar.xz | |
google/eve: Set rise/fall timing values for I2C bus 1
Apply the measured rise and fall times for I2C bus 1 on Eve
so it can be tuned properly for 400KHz operation.
BUG=chrome-os-partner:63020
TEST=verify I2C1 bus speed with a scope
Change-Id: I32b5aa460ea35aadca7f3d52324a64880764919f
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18396
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/eve/devicetree.cb | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index dfe7281d8d..c600b5fde2 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -168,8 +168,12 @@ chip soc/intel/skylake register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # Audio # Enable I2C1 bus early for TPM access - register "i2c[1].early_init" = "1" - register "i2c[1].speed" = "I2C_SPEED_FAST" + register "i2c[1]" = "{ + .early_init = 1, + .speed = I2C_SPEED_FAST, + .rise_time_ns = 88, + .fall_time_ns = 32, + }" # Must leave UART0 enabled or SD/eMMC will not work as PCI register "SerialIoDevMode" = "{ |