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| author | You-Cheng Syu <youcheng@google.com> | 2019-04-09 12:55:55 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-04-09 17:23:59 +0000 |
| commit | cc86d8921b7d285fd0b5841acfeca4ee12be3b3d (patch) | |
| tree | c444a7cb7ff159b170b04aae47a2dce9da08cacd /src/mainboard | |
| parent | 61d365fafdb2100aabf4d39bf525e5364d1db5e8 (diff) | |
| download | coreboot-cc86d8921b7d285fd0b5841acfeca4ee12be3b3d.tar.xz | |
google/kukui: Configure AP_IN_SLEEP_L correctly
This pin should be set to its alternative function SRCLKENA0 instead of
GPIO, so that SPM (a power management component of MT8183) can control
it.
BUG=b:113367227
BRANCH=none
TEST=1. Boot. Run 'powerinfo' in EC console and see power state in S0.
2. Run 'powerd_dbus_suspend --wakeup_timeout=10', and then
run 'powerinfo' in EC console and see power state in S3.
3. Wait until AP resume.
4. Run 'powerinfo' in EC console and see power state back to S0.
Change-Id: I0a7e34f95381dec17eb6d166d6552c12e021bd9a
Signed-off-by: You-Cheng Syu <youcheng@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32120
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/kukui/early_init.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/src/mainboard/google/kukui/early_init.c b/src/mainboard/google/kukui/early_init.c index a16a335bc4..1193bb3fe9 100644 --- a/src/mainboard/google/kukui/early_init.c +++ b/src/mainboard/google/kukui/early_init.c @@ -32,8 +32,7 @@ void mainboard_early_init(void) setup_chromeos_gpios(); - /* Declare we are in S0 */ - gpio_output(AP_IN_SLEEP_L, 1); + gpio_set_mode(AP_IN_SLEEP_L, PAD_SRCLKENA0_FUNC_SRCLKENA0); mtk_spi_init(CONFIG_DRIVER_TPM_SPI_BUS, SPI_PAD0_MASK, 1 * MHz); gpio_eint_configure(CR50_IRQ, IRQ_TYPE_EDGE_RISING); |