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authorSumeet Pawnikar <sumeet.r.pawnikar@intel.com>2019-03-19 16:25:24 +0530
committerPatrick Georgi <pgeorgi@google.com>2019-03-28 06:38:51 +0000
commite2ac5b7a36cd0583a6b62dac4f8dae5529f44b74 (patch)
treed2cec82515eb0bbc4a8df9e19ea56777aadb8f81 /src/mainboard
parent9d4a16953243c45d643e6a1e4e412e8d7137eeb2 (diff)
downloadcoreboot-e2ac5b7a36cd0583a6b62dac4f8dae5529f44b74.tar.xz
mb/google/hatch/variants: Add DPTF based Fan control
This adds DPTF based Fan speed control for CML based Hatch system. BUG=None BRANCH=None TEST=Built and tested fan speed with different temperatures Change-Id: I3c2a679dc67eecb17098ce0f0c9703c679473a2d Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31980 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/hatch/variants/baseboard/include/baseboard/acpi/dptf.asl57
1 files changed, 57 insertions, 0 deletions
diff --git a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/acpi/dptf.asl b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/acpi/dptf.asl
index 6e818f6083..1384ccfeb7 100644
--- a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/acpi/dptf.asl
+++ b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/acpi/dptf.asl
@@ -15,18 +15,34 @@
#define DPTF_CPU_PASSIVE 95
#define DPTF_CPU_CRITICAL 105
+#define DPTF_CPU_ACTIVE_AC0 87
+#define DPTF_CPU_ACTIVE_AC1 85
+#define DPTF_CPU_ACTIVE_AC2 83
+#define DPTF_CPU_ACTIVE_AC3 80
+#define DPTF_CPU_ACTIVE_AC4 75
#define DPTF_TSR0_SENSOR_ID 1
#define DPTF_TSR0_SENSOR_NAME "Thermal Sensor 1"
#define DPTF_TSR0_PASSIVE 65
#define DPTF_TSR0_CRITICAL 75
+#define DPTF_TSR0_ACTIVE_AC0 50
+#define DPTF_TSR0_ACTIVE_AC1 47
+#define DPTF_TSR0_ACTIVE_AC2 45
+#define DPTF_TSR0_ACTIVE_AC3 42
+#define DPTF_TSR0_ACTIVE_AC4 39
#define DPTF_TSR1_SENSOR_ID 2
#define DPTF_TSR1_SENSOR_NAME "Thermal Sensor 2"
#define DPTF_TSR1_PASSIVE 65
#define DPTF_TSR1_CRITICAL 75
+#define DPTF_TSR1_ACTIVE_AC0 50
+#define DPTF_TSR1_ACTIVE_AC1 47
+#define DPTF_TSR1_ACTIVE_AC2 45
+#define DPTF_TSR1_ACTIVE_AC3 42
+#define DPTF_TSR1_ACTIVE_AC4 39
#define DPTF_ENABLE_CHARGER
+#define DPTF_ENABLE_FAN_CONTROL
/* Charger performance states, board-specific values from charger and EC */
Name (CHPS, Package () {
@@ -36,6 +52,47 @@ Name (CHPS, Package () {
Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */
})
+/* DFPS: Fan Performance States */
+Name (DFPS, Package () {
+ 0, // Revision
+ /*
+ * TODO : Need to update this Table after characterization.
+ * These are initial reference values.
+ */
+ /* Control, Trip Point, Speed, NoiseLevel, Power */
+ Package () {90, 0xFFFFFFFF, 6700, 220, 2200},
+ Package () {80, 0xFFFFFFFF, 5800, 180, 1800},
+ Package () {70, 0xFFFFFFFF, 5000, 145, 1450},
+ Package () {60, 0xFFFFFFFF, 4900, 115, 1150},
+ Package () {50, 0xFFFFFFFF, 3838, 90, 900},
+ Package () {40, 0xFFFFFFFF, 2904, 55, 550},
+ Package () {30, 0xFFFFFFFF, 2337, 30, 300},
+ Package () {20, 0xFFFFFFFF, 1608, 15, 150},
+ Package () {10, 0xFFFFFFFF, 800, 10, 100},
+ Package () {0, 0xFFFFFFFF, 0, 0, 50}
+})
+
+Name (DART, Package () {
+ /* Fan effect on CPU */
+ 0, // Revision
+ Package () {
+ /*
+ * Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6,
+ * AC7, AC8, AC9
+ */
+ \_SB.DPTF.TFN1, \_SB.PCI0.TCPU, 100, 90, 69, 56, 46, 36, 0, 0,
+ 0, 0, 0
+ },
+ Package () {
+ \_SB.DPTF.TFN1, \_SB.DPTF.TSR0, 100, 90, 69, 56, 46, 36, 0, 0,
+ 0, 0, 0
+ },
+ Package () {
+ \_SB.DPTF.TFN1, \_SB.DPTF.TSR1, 100, 90, 69, 56, 46, 36, 0, 0,
+ 0, 0, 0
+ }
+})
+
Name (DTRT, Package () {
/* CPU Throttle Effect on CPU */
Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 },