diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2016-08-21 12:19:25 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-08-23 15:46:03 +0200 |
| commit | e53e488cf118ce4842fc31fbf38529f22053333c (patch) | |
| tree | 6d12329b9b85ce3640959175ee36d38cd15c95bd /src/mainboard | |
| parent | 0638b60590731a9cf3b1200ec6a1bc185085eb6c (diff) | |
| download | coreboot-e53e488cf118ce4842fc31fbf38529f22053333c.tar.xz | |
src/mainboard: Remove unnecessary whitespace before "\n"
Change-Id: I9789b0b3339435fbe30c69221826bf23c9b3c77b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16283
Tested-by: build bot (Jenkins)
Reviewed-by: Omar Pakker
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/amd/bettong/romstage.c | 4 | ||||
| -rw-r--r-- | src/mainboard/amd/db-ft3b-lc/romstage.c | 4 | ||||
| -rw-r--r-- | src/mainboard/amd/lamar/romstage.c | 4 | ||||
| -rw-r--r-- | src/mainboard/amd/olivehillplus/romstage.c | 4 | ||||
| -rw-r--r-- | src/mainboard/bap/ode_e21XX/romstage.c | 4 | ||||
| -rw-r--r-- | src/mainboard/iwave/iWRainbowG6/romstage.c | 2 |
6 files changed, 11 insertions, 11 deletions
diff --git a/src/mainboard/amd/bettong/romstage.c b/src/mainboard/amd/bettong/romstage.c index b0ec8fdc19..c3e2aa4b62 100644 --- a/src/mainboard/amd/bettong/romstage.c +++ b/src/mainboard/amd/bettong/romstage.c @@ -52,8 +52,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Load MPB */ val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); + printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x37); AGESAWRAPPER(amdinitreset); diff --git a/src/mainboard/amd/db-ft3b-lc/romstage.c b/src/mainboard/amd/db-ft3b-lc/romstage.c index c64fe4e3bc..f69e188892 100644 --- a/src/mainboard/amd/db-ft3b-lc/romstage.c +++ b/src/mainboard/amd/db-ft3b-lc/romstage.c @@ -65,8 +65,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Load MPB */ val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); + printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x37); AGESAWRAPPER(amdinitreset); diff --git a/src/mainboard/amd/lamar/romstage.c b/src/mainboard/amd/lamar/romstage.c index bcf49e064e..f0845821aa 100644 --- a/src/mainboard/amd/lamar/romstage.c +++ b/src/mainboard/amd/lamar/romstage.c @@ -75,8 +75,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Load MPB */ val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); + printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x37); AGESAWRAPPER(amdinitreset); diff --git a/src/mainboard/amd/olivehillplus/romstage.c b/src/mainboard/amd/olivehillplus/romstage.c index a5c529e7c5..6d1e4ea31f 100644 --- a/src/mainboard/amd/olivehillplus/romstage.c +++ b/src/mainboard/amd/olivehillplus/romstage.c @@ -65,8 +65,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Load MPB */ val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); + printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); /* * This refers to LpcClkDrvSth settling time. Without this setting, processor diff --git a/src/mainboard/bap/ode_e21XX/romstage.c b/src/mainboard/bap/ode_e21XX/romstage.c index 8466e251db..e45464e39d 100644 --- a/src/mainboard/bap/ode_e21XX/romstage.c +++ b/src/mainboard/bap/ode_e21XX/romstage.c @@ -69,8 +69,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Load MPB */ val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); + printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x37); AGESAWRAPPER(amdinitreset); diff --git a/src/mainboard/iwave/iWRainbowG6/romstage.c b/src/mainboard/iwave/iWRainbowG6/romstage.c index a6c5a715c3..9750d082b3 100644 --- a/src/mainboard/iwave/iWRainbowG6/romstage.c +++ b/src/mainboard/iwave/iWRainbowG6/romstage.c @@ -259,7 +259,7 @@ int selectcard(void) { int i; - printk(BIOS_DEBUG, "%s", "\r\nCase 9....... \n\r"); + printk(BIOS_DEBUG, "%s", "\r\nCase 9.......\r\n"); // send the length byte and command code through RFID interface transaction1(RFID_ADDR); |