soc/intel/skylake: Add PcieRpClkSrcNumber UPD configuartion support

New UPD PcieRpClkSrcNumber introduced in FSP V2.9.2 to configure
clock source number of PCIe root ports. This UPD array is set to clock
source number(0-6) for all the enabled PCIe root ports, invalid(0x1F)
is set for disabled PCIe root ports.

BUG=b:70252901
BRANCH=None
TEST= Perform the following
1. Build and boot soraka
2. Verify PCIe devices list using lspci command
3. Perform Basic Assurance Test(BAT) on soraka

Change-Id: I95ca0d893338100b7e4d7d0b76c076ed7e2b040e
Signed-off-by: Divya Chellap <divya.chellappa@intel.com>
Reviewed-on: https://review.coreboot.org/22947
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>

8 files changed, 45 insertions, 1 deletions

diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb
index a0b0ea6194..2880066873 100644
--- a/src/mainboard/google/eve/devicetree.cb
+++ b/src/mainboard/google/eve/devicetree.cb
@@ -146,6 +146,8 @@ chip soc/intel/skylake
 	register "PcieRpClkReqNumber[0]" = "1"
 	register "PcieRpAdvancedErrorReporting[0]" = "1"
 	register "PcieRpLtrEnable[0]" = "1"
+	#RP 1 uses CLK SRC 1
+	register "PcieRpClkSrcNumber[0]" = "1"
 
 	# Enable Root port 5 with SRCCLKREQ4#
 	register "PcieRpEnable[4]" = "1"
@@ -153,6 +155,8 @@ chip soc/intel/skylake
 	register "PcieRpClkReqNumber[4]" = "4"
 	register "PcieRpAdvancedErrorReporting[4]" = "1"
 	register "PcieRpLtrEnable[4]" = "1"
+	#RP 5 uses CLK SRC 4
+	register "PcieRpClkSrcNumber[4]" = "4"
 
 	register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)"	# Type-C Port 1
 	register "usb2_ports[1]" = "USB2_PORT_FLEX(OC_SKIP)"	# Camera
diff --git a/src/mainboard/google/fizz/devicetree.cb b/src/mainboard/google/fizz/devicetree.cb
index 1ee54aaa60..59a80faa50 100644
--- a/src/mainboard/google/fizz/devicetree.cb
+++ b/src/mainboard/google/fizz/devicetree.cb
@@ -178,6 +178,8 @@ chip soc/intel/skylake
 	register "PcieRpAdvancedErrorReporting[2]" = "1"
 	# RP 3, Enable Latency Tolerance Reporting Mechanism
 	register "PcieRpLtrEnable[2]" = "1"
+	# RP 3 uses uses CLK SRC 0
+	register "PcieRpClkSrcNumber[2]" = "0"
 
 	# Enable Root port 4(x1) for WLAN.
 	register "PcieRpEnable[3]" = "1"
@@ -189,6 +191,8 @@ chip soc/intel/skylake
 	register "PcieRpAdvancedErrorReporting[3]" = "1"
 	# RP 4, Enable Latency Tolerance Reporting Mechanism
 	register "PcieRpLtrEnable[3]" = "1"
+	# RP 4 uses uses CLK SRC 5
+	register "PcieRpClkSrcNumber[3]" = "5"
 
 	# Enable Root port 5(x4) for NVMe.
 	register "PcieRpEnable[4]" = "1"
@@ -200,6 +204,8 @@ chip soc/intel/skylake
 	register "PcieRpAdvancedErrorReporting[4]" = "1"
 	# RP 5, Enable Latency Tolerance Reporting Mechanism
 	register "PcieRpLtrEnable[4]" = "1"
+	# RP 5 uses CLK SRC 1
+	register "PcieRpClkSrcNumber[4]" = "1"
 
 	# Enable Root port 9 for BtoB.
 	register "PcieRpEnable[8]" = "1"
@@ -211,6 +217,8 @@ chip soc/intel/skylake
 	register "PcieRpAdvancedErrorReporting[8]" = "1"
 	# RP 9, Enable Latency Tolerance Reporting Mechanism
 	register "PcieRpLtrEnable[8]" = "1"
+	# RP 9 uses uses CLK SRC 2
+	register "PcieRpClkSrcNumber[8]" = "2"
 
 	register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)"	# Type-C
 	register "usb2_ports[1]" = "USB2_PORT_MID(OC3)"		# Type-A Rear
diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
index 2ddf22a948..aaf6ea2b57 100644
--- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
@@ -156,6 +156,8 @@ chip soc/intel/skylake
 	register "PcieRpAdvancedErrorReporting[0]" = "1"
 	# RP 1, Enable Latency Tolerance Reporting Mechanism
 	register "PcieRpLtrEnable[0]" = "1"
+	# RP 1 uses uses CLK SRC 1
+	register "PcieRpClkSrcNumber[0]" = "1"
 
 	register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)"	# Type-C Port 1
 	register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A Port
diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb
index 4f88f707e1..5e23d45a5f 100644
--- a/src/mainboard/google/poppy/variants/nami/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb
@@ -148,11 +148,13 @@ chip soc/intel/skylake
 	#  PcieRpEnable:                 Enable root port
 	#  PcieRpClkReqSupport:          Enable CLKREQ#
 	#  PcieRpClkReqNumber:           Uses SRCCLKREQ1#
+	#  PcieRpClkSrcNumber:           Uses 1
 	#  PcieRpAdvancedErrorReporting: Enable Advanced Error Reporting
 	#  PcieRpLtrEnable:              Enable Latency Tolerance Reporting Mechanism
 	register "PcieRpEnable[3]" = "1"
 	register "PcieRpClkReqSupport[3]" = "1"
 	register "PcieRpClkReqNumber[3]" = "1"
+	register "PcieRpClkSrcNumber[3]" = "1"
 	register "PcieRpAdvancedErrorReporting[3]" = "1"
 	register "PcieRpLtrEnable[3]" = "1"
 
@@ -160,11 +162,13 @@ chip soc/intel/skylake
 	#  PcieRpEnable:                 Enable root port
 	#  PcieRpClkReqSupport:          Enable CLKREQ#
 	#  PcieRpClkReqNumber:           Uses SRCCLKREQ3#
+	#  PcieRpClkSrcNumber:           Uses 3
 	#  PcieRpAdvancedErrorReporting: Enable Advanced Error Reporting
 	#  PcieRpLtrEnable:              Enable Latency Tolerance Reporting Mechanism
 	register "PcieRpEnable[4]" = "1"
 	register "PcieRpClkReqSupport[4]" = "1"
 	register "PcieRpClkReqNumber[4]" = "3"
+	register "PcieRpClkSrcNumber[4]" = "3"
 	register "PcieRpAdvancedErrorReporting[4]" = "1"
 	register "PcieRpLtrEnable[4]" = "1"
 
@@ -172,11 +176,13 @@ chip soc/intel/skylake
 	#  PcieRpEnable:                 Enable root port
 	#  PcieRpClkReqSupport:          Enable CLKREQ#
 	#  PcieRpClkReqNumber:           Uses SRCCLKREQ2#
+	#  PcieRpClkSrcNumber:           Uses 2
 	#  PcieRpAdvancedErrorReporting: Enable Advanced Error Reporting
 	#  PcieRpLtrEnable:              Enable Latency Tolerance Reporting Mechanism
 	register "PcieRpEnable[8]" = "1"
 	register "PcieRpClkReqSupport[8]" = "1"
 	register "PcieRpClkReqNumber[8]" = "2"
+	register "PcieRpClkSrcNumber[8]" = "2"
 	register "PcieRpAdvancedErrorReporting[8]" = "1"
 	register "PcieRpLtrEnable[8]" = "1"
 
diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
index 50137896aa..a548ac98fd 100644
--- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
@@ -157,6 +157,8 @@ chip soc/intel/skylake
 	register "PcieRpClkReqSupport[0]" = "1"
 	# RP 1 uses SRCCLKREQ1#
 	register "PcieRpClkReqNumber[0]" = "1"
+        # RP 1 uses uses CLK SRC 1
+        register "PcieRpClkSrcNumber[0]" = "1"
 	# RP 1, Enable Advanced Error Reporting
 	register "PcieRpAdvancedErrorReporting[0]" = "1"
 	# RP 1, Enable Latency Tolerance Reporting Mechanism
diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb
index 22349d6984..3bcda3cc10 100644
--- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb
@@ -156,6 +156,8 @@ chip soc/intel/skylake
 	register "PcieRpAdvancedErrorReporting[0]" = "1"
 	# RP 1, Enable Latency Tolerance Reporting Mechanism
 	register "PcieRpLtrEnable[0]" = "1"
+	# RP 1 uses uses CLK SRC 1
+	register "PcieRpClkSrcNumber[0]" = "1"
 
 	register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)"	# Type-C Port 1
 	register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A Port
diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb b/src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb
index 0d2bd0f397..a8e835e95c 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb
@@ -138,16 +138,22 @@ chip soc/intel/skylake
 	register "PcieRpEnable[0]" = "1"
 	register "PcieRpClkReqSupport[0]" = "1"
 	register "PcieRpClkReqNumber[0]" = "2"
+	# RP1, uses uses CLK SRC 2
+	register "PcieRpClkSrcNumber[0]" = "2"
 
 	# PCIE Port 5 x1 -> SLOT2/LAN
 	register "PcieRpEnable[4]" = "1"
 	register "PcieRpClkReqSupport[4]" = "1"
 	register "PcieRpClkReqNumber[4]" = "3"
+	# RP5, uses uses CLK SRC 3
+	register "PcieRpClkSrcNumber[4]" = "3"
 
 	# PCIE Port 6 x1 -> SLOT3
 	register "PcieRpEnable[5]" = "1"
 	register "PcieRpClkReqSupport[5]" = "1"
 	register "PcieRpClkReqNumber[5]" = "1"
+	# RP6, uses uses CLK SRC 1
+	register "PcieRpClkSrcNumber[5]" = "1"
 
 	# PCIE Port 7 Disabled
 	# PCIE Port 8 Disabled
@@ -155,11 +161,15 @@ chip soc/intel/skylake
 	register "PcieRpEnable[8]" = "1"
 	register "PcieRpClkReqSupport[8]" = "1"
 	register "PcieRpClkReqNumber[8]" = "5"
+	# RP9, uses uses CLK SRC 5
+	register "PcieRpClkSrcNumber[8]" = "5"
 
 	# PCIE Port 10 x1 -> WiGig
 	register "PcieRpEnable[9]" = "1"
 	register "PcieRpClkReqSupport[9]" = "1"
 	register "PcieRpClkReqNumber[9]" = "4"
+	# RP10, uses uses CLK SRC 4
+	register "PcieRpClkSrcNumber[9]" = "4"
 
 	# USB 2.0 Enable all ports
 	register "usb2_ports[0]" = "USB2_PORT_MAX(OC0)"		# TYPE-A Port
diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/devicetree.cb b/src/mainboard/intel/kblrvp/variants/rvp7/devicetree.cb
index 6f45a46a7d..5c41f22d8a 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp7/devicetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/rvp7/devicetree.cb
@@ -148,13 +148,23 @@ chip soc/intel/skylake
 	register "PcieRpClkReqSupport[5]" = "1"
 	register "PcieRpClkReqSupport[8]" = "1"
 
-	# RP 9 uses SRCCLKREQ5#
+	# RP 3 uses SRCCLKREQ5#
 	register "PcieRpClkReqNumber[2]" = "5"
 	register "PcieRpClkReqNumber[3]" = "2"
 	register "PcieRpClkReqNumber[4]" = "3"
 	register "PcieRpClkReqNumber[5]" = "4"
 	register "PcieRpClkReqNumber[8]" = "1"
 
+	# RP 3 uses uses CLK SRC 5#
+	register "PcieRpClkSrcNumber[2]" = "5"
+	# RP 4 uses uses CLK SRC 2#
+	register "PcieRpClkSrcNumber[3]" = "2"
+	# RP 5 uses uses CLK SRC 3#
+	register "PcieRpClkSrcNumber[4]" = "3"
+	# RP 6 uses uses CLK SRC 4#
+	register "PcieRpClkSrcNumber[5]" = "4"
+	# RP 9 uses uses CLK SRC 1#
+	register "PcieRpClkSrcNumber[8]" = "1"
 
 	# USB 2.0 Enable all ports
         register "usb2_ports[0]" = "USB2_PORT_MAX(OC0)"		# TYPE-A Port