diff options
| author | Lin Huang <hl@rock-chips.com> | 2016-09-21 17:05:43 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2016-10-07 17:33:38 +0200 |
| commit | f08f38883ea1a5c12bd1ece1736e336c20645e7c (patch) | |
| tree | c32dc6a6e53627ee449f9236c74c808272c9a731 /src/mainboard | |
| parent | c9fea5cdec8214703edcea9ea3012f37a37b1c3c (diff) | |
| download | coreboot-f08f38883ea1a5c12bd1ece1736e336c20645e7c.tar.xz | |
google/gru: set W2W_DIFFCS_DLY to 5
PHY_PER_CS_TRAINING is being enabled when DDR frequency >= 666.
For per cs training, the controller should consider the PHY
delay line switch time and there should be more cycles to
switch the delay line, so update the W2W_DIFFCS_DLY_ value
from 0x1 to 0x5.
BRANCH=none
BUG=chrome-os-partner:56940
TEST=do memtester on kevin board, and pass
Change-Id: I00df2d4724b0b77f3e7565809fb35bbd2ff01ea5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c135ea3e33d810ed322d947eb8d512d1ac119cfc
Original-Change-Id: I81b99cbc085769b7028e770509d79bd8d550820b
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/387506
Original-Reviewed-by: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-by: Derek Basehore <dbasehore@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/16721
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard')
4 files changed, 9 insertions, 9 deletions
diff --git a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-200.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-200.c index c8771588ba..533014190b 100644 --- a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-200.c +++ b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-200.c @@ -279,8 +279,8 @@ struct rk3399_sdram_params params = { 0x05050502, /* DENALI_CTL_215_DATA */ 0x02080808, /* DENALI_CTL_216_DATA */ 0x02050202, /* DENALI_CTL_217_DATA */ - 0x02010202, /* DENALI_CTL_218_DATA */ - 0x00010202, /* DENALI_CTL_219_DATA */ + 0x02050202, /* DENALI_CTL_218_DATA */ + 0x00050202, /* DENALI_CTL_219_DATA */ 0x00020202, /* DENALI_CTL_220_DATA */ 0x02010200, /* DENALI_CTL_221_DATA */ 0x00010201, /* DENALI_CTL_222_DATA */ diff --git a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-666.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-666.c index 591924d8a8..4b73cb0154 100644 --- a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-666.c +++ b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-666.c @@ -279,8 +279,8 @@ struct rk3399_sdram_params params = { 0x08080803, /* DENALI_CTL_215_DATA */ 0x08080808, /* DENALI_CTL_216_DATA */ 0x02050203, /* DENALI_CTL_217_DATA */ - 0x02010303, /* DENALI_CTL_218_DATA */ - 0x00010203, /* DENALI_CTL_219_DATA */ + 0x02050303, /* DENALI_CTL_218_DATA */ + 0x00050203, /* DENALI_CTL_219_DATA */ 0x00020202, /* DENALI_CTL_220_DATA */ 0x03020400, /* DENALI_CTL_221_DATA */ 0x00020401, /* DENALI_CTL_222_DATA */ diff --git a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800.c index b7386445af..3056e55b20 100644 --- a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800.c +++ b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800.c @@ -279,8 +279,8 @@ struct rk3399_sdram_params params = { 0x0a0a0a03, /* DENALI_CTL_215_DATA */ 0x08080808, /* DENALI_CTL_216_DATA */ 0x02050103, /* DENALI_CTL_217_DATA */ - 0x02010103, /* DENALI_CTL_218_DATA */ - 0x00010103, /* DENALI_CTL_219_DATA */ + 0x02050103, /* DENALI_CTL_218_DATA */ + 0x00050103, /* DENALI_CTL_219_DATA */ 0x00020202, /* DENALI_CTL_220_DATA */ 0x03020500, /* DENALI_CTL_221_DATA */ 0x00020501, /* DENALI_CTL_222_DATA */ diff --git a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-933.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-933.c index 362489b7e5..3947881856 100644 --- a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-933.c +++ b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-933.c @@ -278,9 +278,9 @@ struct rk3399_sdram_params params = { 0x04040001, /* DENALI_CTL_214_DATA */ 0x0c0c0c04, /* DENALI_CTL_215_DATA */ 0x08080808, /* DENALI_CTL_216_DATA */ - 0x02010103, /* DENALI_CTL_217_DATA */ - 0x02010103, /* DENALI_CTL_218_DATA */ - 0x00010103, /* DENALI_CTL_219_DATA */ + 0x02050103, /* DENALI_CTL_217_DATA */ + 0x02050103, /* DENALI_CTL_218_DATA */ + 0x00050103, /* DENALI_CTL_219_DATA */ 0x00020202, /* DENALI_CTL_220_DATA */ 0x06030600, /* DENALI_CTL_221_DATA */ 0x00030603, /* DENALI_CTL_222_DATA */ |