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| author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2015-11-24 14:12:07 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-02-05 22:27:56 +0100 |
| commit | f098a7310a6e1d1e86f3720d10eaa7c0b0687935 (patch) | |
| tree | 29c456dc6130c9a435aca09a68d25711a489ec8b /src/mainboard | |
| parent | 4e543d391592929d3d9a4d16cba7cec6696c8440 (diff) | |
| download | coreboot-f098a7310a6e1d1e86f3720d10eaa7c0b0687935.tar.xz | |
mainboard/asus/kgpe-d16: Add CPB control CMOS option
Change-Id: I28ad2298ad4dfb428dcd41a4f00db88c5e817cd7
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13173
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/asus/kgpe-d16/cmos.default | 1 | ||||
| -rw-r--r-- | src/mainboard/asus/kgpe-d16/cmos.layout | 5 |
2 files changed, 4 insertions, 2 deletions
diff --git a/src/mainboard/asus/kgpe-d16/cmos.default b/src/mainboard/asus/kgpe-d16/cmos.default index a05b9c3745..0e7afb3792 100644 --- a/src/mainboard/asus/kgpe-d16/cmos.default +++ b/src/mainboard/asus/kgpe-d16/cmos.default @@ -17,6 +17,7 @@ interleave_nodes = Disable interleave_memory_channels = Enable cpu_c_states = Enable cpu_cc6_state = Enable +cpu_core_boost = Enable sata_ahci_mode = Enable sata_alpm = Disable maximum_p_state_limit = 0xf diff --git a/src/mainboard/asus/kgpe-d16/cmos.layout b/src/mainboard/asus/kgpe-d16/cmos.layout index d1c070215b..075388e20a 100644 --- a/src/mainboard/asus/kgpe-d16/cmos.layout +++ b/src/mainboard/asus/kgpe-d16/cmos.layout @@ -48,8 +48,9 @@ entries 476 1 e 1 l3_cache_partitioning 477 1 e 1 ieee1394_controller 478 1 e 1 iommu -479 1 e 1 experimental_memory_speed_boost -480 1 r 0 allow_spd_nvram_cache_restore +479 1 e 1 cpu_core_boost +480 1 e 1 experimental_memory_speed_boost +481 1 r 0 allow_spd_nvram_cache_restore 728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers |