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| author | V Sowmya <v.sowmya@intel.com> | 2020-12-14 09:22:45 +0530 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2020-12-17 06:23:41 +0000 |
| commit | f0a9142b24889087a61c66ccf3a39d7a93563e02 (patch) | |
| tree | 03b9306341e31d96977594aed42144bcfefe387f /src/mainboard | |
| parent | 16f213a499a033627a4897f808110759cf3d52fa (diff) | |
| download | coreboot-f0a9142b24889087a61c66ccf3a39d7a93563e02.tar.xz | |
mb/intel/adlrvp: Enable PCIEXP_HOTPLUG for TCSS TBT/USB4 ports
This change enables PCIEXP_HOTPLUG to support resource allocation for
TCSS TBT/USB4 ports.
Referred from TGLRVP -> https://review.coreboot.org/c/coreboot/+/41543
Change-Id: I5f883dac0d7e5fa84ad2e1683f84c933a90cea51
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/intel/adlrvp/Kconfig | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/src/mainboard/intel/adlrvp/Kconfig b/src/mainboard/intel/adlrvp/Kconfig index b6d3ff3cdb..369ce21e05 100644 --- a/src/mainboard/intel/adlrvp/Kconfig +++ b/src/mainboard/intel/adlrvp/Kconfig @@ -15,6 +15,7 @@ config BOARD_SPECIFIC_OPTIONS select SOC_INTEL_ALDERLAKE select HAVE_SPD_IN_CBFS select DRIVERS_SOUNDWIRE_ALC711 + select PCIEXP_HOTPLUG config CHROMEOS bool @@ -77,6 +78,18 @@ config ADL_INTEL_EC select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC endchoice +config PCIEXP_HOTPLUG_BUSES + int + default 42 + +config PCIEXP_HOTPLUG_MEM + hex + default 0xc200000 # 194 MiB + +config PCIEXP_HOTPLUG_PREFETCH_MEM + hex + default 0x1c000000 # 448 MiB + config VBOOT select VBOOT_LID_SWITCH select VBOOT_MOCK_SECDATA |