diff options
| author | Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> | 2007-11-12 11:14:10 +0000 |
|---|---|---|
| committer | Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> | 2007-11-12 11:14:10 +0000 |
| commit | 390648df6480fff86acd2a51600fc0352aef7597 (patch) | |
| tree | fc627161490e0ad881d4ad9b26c1abdd6323d217 /src/mainboard | |
| parent | 18517e8a1fc9fdbf56a01a0122ec5e31e48fa2aa (diff) | |
| download | coreboot-390648df6480fff86acd2a51600fc0352aef7597.tar.xz | |
Fix the remaining issues with GA-M57SLI Super I/O GPIO configuration.
With this patch, flashing the parallel EEPROM on board revisions 1.x
finally works. Flashing the serial EEPROM of board revisions 2.x is just
one patch away.
Torsten Duwe says:
Flash erase on my board was failing reliably. Now it works!
Andreas B. Mundt says:
For the first time I was able to write with flashrom and LB.
$flashrom -Vv --write linuxbios.rom
[...]
Vendor ID: GIGABYTE, part ID: m57sli
Found chipset "NVIDIA MCP55", enabling flash write... OK.
[...]
SST49LF040B found at physical address 0xfff80000.
Flash part is SST49LF040B (512 KB).
LinuxBIOS last image size (not ROM size) is 4096 bytes.
Manufacturer: GIGABYTE
Mainboard ID: m57sli
This firmware image matches this motherboard.
Programming page: 0007 at address: 0x00070000
Verifying flash... VERIFIED.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Torsten Duwe <duwe@lst.de>
Tested-by: Andreas B. Mundt <andi.mundt@web.de>
Tested-by: Torsten Duwe <duwe@lst.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2955 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/gigabyte/m57sli/Config.lb | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/src/mainboard/gigabyte/m57sli/Config.lb b/src/mainboard/gigabyte/m57sli/Config.lb index 8d6ab1ba61..8fece774e9 100644 --- a/src/mainboard/gigabyte/m57sli/Config.lb +++ b/src/mainboard/gigabyte/m57sli/Config.lb @@ -282,17 +282,17 @@ chip northbridge/amd/amdk8/root_complex # pin 13 is GP35 irq 0x27 = 0x20 # pin 70 is not GP46 - #0x28 = 0x0 + #irq 0x28 = 0x0 # pin 6,3,128,127,126 is GP63,64,65,66,67 irq 0x29 = 0x81 # Enable FAN_CTL/FAN_TAC set to 5 (pin 21,23), enable FAN_CTL/FAN_TAC set to 4 (pin 20,22), pin 48 is PCIRST5#, pin91 is PCIRSTIN#, VIN7 is internal voltage divider for VCCH5V, pin 95 is ATXPG, VIN3 is internal voltage divider for VCC5V - #0x2c = 0x1f + #irq 0x2c = 0x1f # Simple I/O base io 0x62 = 0x800 # Serial Flash I/O (SPI only) #io 0x64 = 0x820 # watch dog force timeout (parallel flash only) - #0x71 = 0x1 + #irq 0x71 = 0x1 # No WDT interrupt irq 0x72 = 0x0 # GPIO pin set 1 disable internal pullup @@ -300,23 +300,23 @@ chip northbridge/amd/amdk8/root_complex # GPIO pin set 5 enable internal pullup irq 0xbc = 0x01 # SIO pin set 1 alternate function - #0xc0 = 0x0 + #irq 0xc0 = 0x0 # SIO pin set 2 mixed function irq 0xc1 = 0x43 # SIO pin set 3 mixed function irq 0xc2 = 0x20 # SIO pin set 4 alternate function - #0xc3 = 0x0 + #irq 0xc3 = 0x0 # SIO pin set 1 input mode - #0xc8 = 0x0 + #irq 0xc8 = 0x0 # SIO pin set 2 mixed input/output mode irq 0xc9 = 0x0 # SIO pin set 4 input mode - #0xcb = 0x0 + #irq 0xcb = 0x0 # Generate SMI# on EC IRQ - #0xf0 = 0x10 + #irq 0xf0 = 0x10 # SMI# level trigger - #0xf1 = 0x40 + #irq 0xf1 = 0x40 # HWMON alert beep pin location irq 0xf6 = 0x28 end |