diff options
| author | Zhuohao Lee <zhuohao@chromium.org> | 2018-08-02 23:47:55 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-08-06 07:55:04 +0000 |
| commit | 3d1bd1f042d9d552d752ea4ed072da34337b84fc (patch) | |
| tree | 67e21f12c40beb0c632c466e69f352f610502924 /src/mainboard | |
| parent | bd6f00f7a3b01cc3890de911fda437a30398a9cb (diff) | |
| download | coreboot-3d1bd1f042d9d552d752ea4ed072da34337b84fc.tar.xz | |
mb/google/poppy/variants/rammus: add memory configuration
Add memory configuration based on the proto board schematics
BUG=b:111579386
BRANCH=Master
TEST=Build pass
Change-Id: I45efdc7893b5bcbca0de6e932e1452cc1a2ff028
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/27806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/poppy/variants/rammus/Makefile.inc | 3 | ||||
| -rw-r--r-- | src/mainboard/google/poppy/variants/rammus/memory.c | 49 |
2 files changed, 52 insertions, 0 deletions
diff --git a/src/mainboard/google/poppy/variants/rammus/Makefile.inc b/src/mainboard/google/poppy/variants/rammus/Makefile.inc index 98464af429..edfaceaa32 100644 --- a/src/mainboard/google/poppy/variants/rammus/Makefile.inc +++ b/src/mainboard/google/poppy/variants/rammus/Makefile.inc @@ -1,2 +1,5 @@ SPD_SOURCES = empty # 0b0000 + +romstage-y += memory.c + ramstage-y += nhlt.c diff --git a/src/mainboard/google/poppy/variants/rammus/memory.c b/src/mainboard/google/poppy/variants/rammus/memory.c new file mode 100644 index 0000000000..92e66bd9fb --- /dev/null +++ b/src/mainboard/google/poppy/variants/rammus/memory.c @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/variants.h> + +/* DQ byte map */ +static const u8 dq_map[][12] = { + { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, + 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, + { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, + 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } +}; + +/* DQS CPU<>DRAM map */ +static const u8 dqs_map[][8] = { + { 0, 1, 3, 2, 4, 5, 6, 7 }, + { 1, 0, 4, 5, 2, 3, 6, 7 }, +}; + +/* Rcomp resistor */ +static const u16 rcomp_resistor[] = { 200, 81, 162 }; + +/* Rcomp target */ +static const u16 rcomp_target[] = { 100, 40, 40, 23, 40 }; + +void variant_memory_params(struct memory_params *p) +{ + p->type = MEMORY_LPDDR3; + p->dq_map = dq_map; + p->dq_map_size = sizeof(dq_map); + p->dqs_map = dqs_map; + p->dqs_map_size = sizeof(dqs_map); + p->rcomp_resistor = rcomp_resistor; + p->rcomp_resistor_size = sizeof(rcomp_resistor); + p->rcomp_target = rcomp_target; + p->rcomp_target_size = sizeof(rcomp_target); +} |