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authorStefan Reinauer <stepan@coresystems.de>2010-05-25 17:09:05 +0000
committerStefan Reinauer <stepan@openbios.org>2010-05-25 17:09:05 +0000
commit7e00a44b773ba16b72fa1ca69825407be0c98ad5 (patch)
tree57c5c75b90ccf375ae4cc30cc58581b8b301a6ca /src/mainboard
parent75a05dc0b91fb5748bb4f8b0eee9cee168c2cda1 (diff)
downloadcoreboot-7e00a44b773ba16b72fa1ca69825407be0c98ad5.tar.xz
also rename the config option.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5588 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/getac/p470/romstage.c4
-rw-r--r--src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c2
-rw-r--r--src/mainboard/gigabyte/ga_2761gxdk/romstage.c4
-rw-r--r--src/mainboard/gigabyte/m57sli/ap_romstage.c2
-rw-r--r--src/mainboard/gigabyte/m57sli/romstage.c4
-rw-r--r--src/mainboard/intel/d945gclf/romstage.c4
-rw-r--r--src/mainboard/kontron/986lcd-m/romstage.c4
-rw-r--r--src/mainboard/msi/ms7260/ap_romstage.c2
-rw-r--r--src/mainboard/msi/ms7260/romstage.c4
-rw-r--r--src/mainboard/msi/ms9652_fam10/Kconfig2
-rw-r--r--src/mainboard/msi/ms9652_fam10/romstage.c4
-rw-r--r--src/mainboard/nvidia/l1_2pvv/ap_romstage.c2
-rw-r--r--src/mainboard/nvidia/l1_2pvv/romstage.c4
-rw-r--r--src/mainboard/roda/rk886ex/romstage.c4
-rw-r--r--src/mainboard/tyan/s2912/ap_romstage.c2
-rw-r--r--src/mainboard/tyan/s2912/romstage.c4
-rw-r--r--src/mainboard/tyan/s2912_fam10/romstage.c4
17 files changed, 28 insertions, 28 deletions
diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c
index 7082bd94a6..c3a0b76713 100644
--- a/src/mainboard/getac/p470/romstage.c
+++ b/src/mainboard/getac/p470/romstage.c
@@ -37,7 +37,7 @@
#include <console/console.h>
#include <cpu/x86/bist.h>
-#if CONFIG_USBDEBUG_DIRECT
+#if CONFIG_USBDEBUG
#define DBGP_DEFAULT 0
#include "southbridge/intel/i82801gx/i82801gx_usb_debug.c"
#include "pc80/usbdebug_serial.c"
@@ -320,7 +320,7 @@ void main(unsigned long bist)
/* Set up the console */
uart_init();
-#if CONFIG_USBDEBUG_DIRECT
+#if CONFIG_USBDEBUG
i82801gx_enable_usbdebug(DBGP_DEFAULT);
early_usbdebug_init();
#endif
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c
index e42a312400..a7a4dbdfaa 100644
--- a/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c
+++ b/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c
@@ -83,7 +83,7 @@ void hardwaremain(int ret_addr)
id = get_node_core_id_x();
- //FIXME: for USBDEBUG_DIRECT you need to make sure dbg_info get assigned in AP
+ //FIXME: for USBDEBUG you need to make sure dbg_info get assigned in AP
print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\n");
train_ram(id.nodeid, sysinfo, sysinfox);
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
index 2eda2089c3..5162000b05 100644
--- a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
+++ b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
@@ -54,7 +54,7 @@
#include "pc80/mc146818rtc_early.c"
#include <console/console.h>
-#if CONFIG_USBDEBUG_DIRECT
+#if CONFIG_USBDEBUG
#include "southbridge/sis/sis966/sis966_enable_usbdebug.c"
#include "pc80/usbdebug_serial.c"
#endif
@@ -199,7 +199,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
-#if CONFIG_USBDEBUG_DIRECT
+#if CONFIG_USBDEBUG
sis966_enable_usbdebug(DBGP_DEFAULT);
early_usbdebug_init();
#endif
diff --git a/src/mainboard/gigabyte/m57sli/ap_romstage.c b/src/mainboard/gigabyte/m57sli/ap_romstage.c
index 8429286bc7..61ca908248 100644
--- a/src/mainboard/gigabyte/m57sli/ap_romstage.c
+++ b/src/mainboard/gigabyte/m57sli/ap_romstage.c
@@ -81,7 +81,7 @@ void hardwaremain(int ret_addr)
id = get_node_core_id_x();
- //FIXME: for USBDEBUG_DIRECT you need to make sure dbg_info get assigned in AP
+ //FIXME: for USBDEBUG you need to make sure dbg_info get assigned in AP
print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\n");
train_ram(id.nodeid, sysinfo, sysinfox);
diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c
index d7a7a3bb4c..18c6e9280e 100644
--- a/src/mainboard/gigabyte/m57sli/romstage.c
+++ b/src/mainboard/gigabyte/m57sli/romstage.c
@@ -52,7 +52,7 @@
#include "pc80/mc146818rtc_early.c"
#include <console/console.h>
-#if CONFIG_USBDEBUG_DIRECT
+#if CONFIG_USBDEBUG
#include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c"
#include "pc80/usbdebug_serial.c"
#endif
@@ -212,7 +212,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
-#if CONFIG_USBDEBUG_DIRECT
+#if CONFIG_USBDEBUG
mcp55_enable_usbdebug(DBGP_DEFAULT);
early_usbdebug_init();
#endif
diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c
index 87f658615b..6f32fe5f86 100644
--- a/src/mainboard/intel/d945gclf/romstage.c
+++ b/src/mainboard/intel/d945gclf/romstage.c
@@ -39,7 +39,7 @@
#include <console/console.h>
#include <cpu/x86/bist.h>
-#if CONFIG_USBDEBUG_DIRECT
+#if CONFIG_USBDEBUG
#define DBGP_DEFAULT 1
#include "southbridge/intel/i82801gx/i82801gx_usb_debug.c"
#include "pc80/usbdebug_serial.c"
@@ -236,7 +236,7 @@ void main(unsigned long bist)
/* Set up the console */
uart_init();
-#if CONFIG_USBDEBUG_DIRECT
+#if CONFIG_USBDEBUG
i82801gx_enable_usbdebug(DBGP_DEFAULT);
early_usbdebug_init();
#endif
diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c
index 4ba6a1afeb..30c118e73b 100644
--- a/src/mainboard/kontron/986lcd-m/romstage.c
+++ b/src/mainboard/kontron/986lcd-m/romstage.c
@@ -48,7 +48,7 @@
#include <console/console.h>
#include <cpu/x86/bist.h>
-#if CONFIG_USBDEBUG_DIRECT
+#if CONFIG_USBDEBUG
#define DBGP_DEFAULT 1
#include <usbdebug.h>
#include "southbridge/intel/i82801gx/i82801gx_usb_debug.c"
@@ -380,7 +380,7 @@ void main(unsigned long bist)
/* Set up the console */
uart_init();
-#if CONFIG_USBDEBUG_DIRECT
+#if CONFIG_USBDEBUG
i82801gx_enable_usbdebug(DBGP_DEFAULT);
early_usbdebug_init();
#endif
diff --git a/src/mainboard/msi/ms7260/ap_romstage.c b/src/mainboard/msi/ms7260/ap_romstage.c
index 246d7afc64..229e9bc397 100644
--- a/src/mainboard/msi/ms7260/ap_romstage.c
+++ b/src/mainboard/msi/ms7260/ap_romstage.c
@@ -67,7 +67,7 @@ void hardwaremain(int ret_addr)
id = get_node_core_id_x();
- /* FIXME: For USBDEBUG_DIRECT you need to make sure dbg_info gets
+ /* FIXME: For USBDEBUG you need to make sure dbg_info gets
* assigned in AP.
*/
print_debug("CODE IN CACHE ON NODE:");
diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c
index 1b827a0dc9..ee2118e59c 100644
--- a/src/mainboard/msi/ms7260/romstage.c
+++ b/src/mainboard/msi/ms7260/romstage.c
@@ -56,7 +56,7 @@
#include "pc80/mc146818rtc_early.c"
#include <console/console.h>
-#if CONFIG_USBDEBUG_DIRECT
+#if CONFIG_USBDEBUG
#include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c"
#include "pc80/usbdebug_serial.c"
#endif
@@ -181,7 +181,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
setup_mb_resource_map();
uart_init();
report_bist_failure(bist); /* Halt upon BIST failure. */
-#if CONFIG_USBDEBUG_DIRECT
+#if CONFIG_USBDEBUG
mcp55_enable_usbdebug(DBGP_DEFAULT);
early_usbdebug_init();
#endif
diff --git a/src/mainboard/msi/ms9652_fam10/Kconfig b/src/mainboard/msi/ms9652_fam10/Kconfig
index 7bbd01c683..499735cfb9 100644
--- a/src/mainboard/msi/ms9652_fam10/Kconfig
+++ b/src/mainboard/msi/ms9652_fam10/Kconfig
@@ -159,7 +159,7 @@ config PCI_ROM_RUN
default y
depends on BOARD_MSI_MS9652_FAM10
-config USBDEBUG_DIRECT
+config USBDEBUG
bool
default n
depends on BOARD_MSI_MS9652_FAM10
diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c
index 1c2a729d4a..9d00a8d92a 100644
--- a/src/mainboard/msi/ms9652_fam10/romstage.c
+++ b/src/mainboard/msi/ms9652_fam10/romstage.c
@@ -45,7 +45,7 @@
#include <cpu/x86/lapic.h>
#include "option_table.h"
#include <console/console.h>
-#if CONFIG_USBDEBUG_DIRECT
+#if CONFIG_USBDEBUG
#include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c"
#include "pc80/usbdebug_serial.c"
#endif
@@ -185,7 +185,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
-#if CONFIG_USBDEBUG_DIRECT
+#if CONFIG_USBDEBUG
mcp55_enable_usbdebug(DBGP_DEFAULT);
early_usbdebug_init();
#endif
diff --git a/src/mainboard/nvidia/l1_2pvv/ap_romstage.c b/src/mainboard/nvidia/l1_2pvv/ap_romstage.c
index cad5252c77..2e7b5aa970 100644
--- a/src/mainboard/nvidia/l1_2pvv/ap_romstage.c
+++ b/src/mainboard/nvidia/l1_2pvv/ap_romstage.c
@@ -81,7 +81,7 @@ void hardwaremain(int ret_addr)
id = get_node_core_id_x();
- //FIXME: for USBDEBUG_DIRECT you need to make sure dbg_info get assigned in AP
+ //FIXME: for USBDEBUG you need to make sure dbg_info get assigned in AP
print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\n");
train_ram(id.nodeid, sysinfo, sysinfox);
diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c
index 572015bf8c..001173657a 100644
--- a/src/mainboard/nvidia/l1_2pvv/romstage.c
+++ b/src/mainboard/nvidia/l1_2pvv/romstage.c
@@ -52,7 +52,7 @@
#include "pc80/mc146818rtc_early.c"
#include <console/console.h>
-#if CONFIG_USBDEBUG_DIRECT
+#if CONFIG_USBDEBUG
#include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c"
#include "pc80/usbdebug_serial.c"
#endif
@@ -198,7 +198,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
-#if CONFIG_USBDEBUG_DIRECT
+#if CONFIG_USBDEBUG
mcp55_enable_usbdebug(DBGP_DEFAULT);
early_usbdebug_init();
#endif
diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c
index 693251922c..eb9df6623c 100644
--- a/src/mainboard/roda/rk886ex/romstage.c
+++ b/src/mainboard/roda/rk886ex/romstage.c
@@ -41,7 +41,7 @@
#include <console/console.h>
#include <cpu/x86/bist.h>
-#if CONFIG_USBDEBUG_DIRECT
+#if CONFIG_USBDEBUG
#define DBGP_DEFAULT 1
#include "southbridge/intel/i82801gx/i82801gx_usb_debug.c"
#include "pc80/usbdebug_serial.c"
@@ -290,7 +290,7 @@ void main(unsigned long bist)
/* Set up the console */
uart_init();
-#if CONFIG_USBDEBUG_DIRECT
+#if CONFIG_USBDEBUG
i82801gx_enable_usbdebug(DBGP_DEFAULT);
early_usbdebug_init();
#endif
diff --git a/src/mainboard/tyan/s2912/ap_romstage.c b/src/mainboard/tyan/s2912/ap_romstage.c
index 41a4a6ee8d..1dff142369 100644
--- a/src/mainboard/tyan/s2912/ap_romstage.c
+++ b/src/mainboard/tyan/s2912/ap_romstage.c
@@ -78,7 +78,7 @@ void hardwaremain(int ret_addr)
id = get_node_core_id_x();
- //FIXME: for USBDEBUG_DIRECT you need to make sure dbg_info get assigned in AP
+ //FIXME: for USBDEBUG you need to make sure dbg_info get assigned in AP
print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\n");
train_ram(id.nodeid, sysinfo, sysinfox);
diff --git a/src/mainboard/tyan/s2912/romstage.c b/src/mainboard/tyan/s2912/romstage.c
index cb2a2e0d4e..822474bcf9 100644
--- a/src/mainboard/tyan/s2912/romstage.c
+++ b/src/mainboard/tyan/s2912/romstage.c
@@ -52,7 +52,7 @@
#include "pc80/mc146818rtc_early.c"
#include <console/console.h>
-#if CONFIG_USBDEBUG_DIRECT
+#if CONFIG_USBDEBUG
#include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c"
#include "pc80/usbdebug_serial.c"
#endif
@@ -192,7 +192,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
-#if CONFIG_USBDEBUG_DIRECT
+#if CONFIG_USBDEBUG
mcp55_enable_usbdebug(DBGP_DEFAULT);
early_usbdebug_init();
#endif
diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c
index 27d51aba25..05beb124f7 100644
--- a/src/mainboard/tyan/s2912_fam10/romstage.c
+++ b/src/mainboard/tyan/s2912_fam10/romstage.c
@@ -45,7 +45,7 @@
#include <cpu/x86/lapic.h>
#include "option_table.h"
#include <console/console.h>
-#if CONFIG_USBDEBUG_DIRECT
+#if CONFIG_USBDEBUG
#include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c"
#include "pc80/usbdebug_serial.c"
#endif
@@ -180,7 +180,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
-#if CONFIG_USBDEBUG_DIRECT
+#if CONFIG_USBDEBUG
mcp55_enable_usbdebug(DBGP_DEFAULT);
early_usbdebug_init();
#endif
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-23 14:23:08 +0000