diff options
author | WANG Siyuan <wangsiyuanbuaa@gmail.com> | 2015-08-18 06:22:22 +0800 |
---|---|---|
committer | Zheng Bao <zheng.bao@amd.com> | 2015-11-20 05:41:41 +0100 |
commit | 839d68f1019f9d1a0e57b1429bf1be4685d5e095 (patch) | |
tree | 3302801f54fec2e14905141ce9b1d0600a378ff7 /src/mainboard | |
parent | 1bb4083859b848b9ffe98ca9fdfbd10adcf482dd (diff) | |
download | coreboot-839d68f1019f9d1a0e57b1429bf1be4685d5e095.tar.xz |
AMD Bettong: refactor PCI interrupt table
1. Use write_pci_int_table to write registers 0xC00/0xC01.
2. Add GPIO, I2C and UART interrupt according
"BKDG for AMD Family 15h Models 60h-6Fh Processors",
50742 Rev 3.01 - July 17, 2015
3. The interrupt valudes are moved from bettong/mptable.c.
All devices work in Windows 10.
Change-Id: Iad13bc02c84a5dfc7c24356436ac560f593304d7
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Reviewed-on: http://review.coreboot.org/11746
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Diffstat (limited to 'src/mainboard')
-rw-r--r-- | src/mainboard/amd/bettong/mainboard.c | 62 | ||||
-rw-r--r-- | src/mainboard/amd/bettong/mptable.c | 54 |
2 files changed, 75 insertions, 41 deletions
diff --git a/src/mainboard/amd/bettong/mainboard.c b/src/mainboard/amd/bettong/mainboard.c index dc5d4385ba..c31f5b7995 100644 --- a/src/mainboard/amd/bettong/mainboard.c +++ b/src/mainboard/amd/bettong/mainboard.c @@ -17,6 +17,65 @@ #include <device/device.h> #include <arch/acpi.h> #include <agesawrapper.h> +#include <southbridge/amd/common/amd_pci_util.h> + +/*********************************************************** + * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. + * This table is responsible for physically routing the PIC and + * IOAPIC IRQs to the different PCI devices on the system. It + * is read and written via registers 0xC00/0xC01 as an + * Index/Data pair. These values are chipset and mainboard + * dependent and should be updated accordingly. + * + * These values are used by the PCI configuration space, + * MP Tables. TODO: Make ACPI use these values too. + */ +const u8 mainboard_picr_data[] = { + [0x00] = 0x03,0x04,0x05,0x07,0x0B,0x0A,0x1F,0x1F, + [0x08] = 0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, + [0x10] = 0x1F,0x1F,0x1F,0x03,0x1F,0x1F,0x1F,0x1F, + [0x18] = 0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00, + [0x28] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + [0x30] = 0x05,0x04,0x05,0x04,0x04,0x05,0x04,0x05, + [0x38] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + [0x40] = 0x04,0x1F,0x00,0x00,0x00,0x00,0x00,0x00, + [0x48] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + [0x50] = 0x03,0x04,0x05,0x07,0x1F,0x1F,0x1F,0x1F, + [0x58] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, + [0x60] = 0x1F,0x1F,0x07,0x1F,0x1F,0x1F,0x1F,0x1F, + [0x68] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, + [0x70] = 0x03,0x0F,0x06,0x0E,0x0A,0x0B,0x1F,0x1F, + [0x78] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, +}; + +const u8 mainboard_intr_data[] = { + [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, + [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, + [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x1F,0x1F,0x10, + [0x18] = 0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00, + [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00, + [0x28] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + [0x30] = 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00, + [0x38] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + [0x40] = 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00, + [0x48] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + [0x50] = 0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00, + [0x58] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + [0x60] = 0x1F,0x1F,0x07,0x00,0x00,0x00,0x00,0x00, + [0x68] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + [0x70] = 0x03,0x0F,0x06,0x0E,0x0A,0x0B,0x1F,0x1F, + [0x78] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +}; + +/* PIRQ Setup */ +static void pirq_setup(void) +{ + intr_data_ptr = mainboard_intr_data; + picr_data_ptr = mainboard_picr_data; +} + + /************************************************* * enable the dedicated function in bettong board. @@ -27,6 +86,9 @@ static void bettong_enable(device_t dev) if (acpi_is_wakeup_s3()) agesawrapper_fchs3earlyrestore(); + + /* Initialize the PIRQ data structures for consumption */ + pirq_setup(); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/amd/bettong/mptable.c b/src/mainboard/amd/bettong/mptable.c index 77eff8cd2c..d77d7e9ab7 100644 --- a/src/mainboard/amd/bettong/mptable.c +++ b/src/mainboard/amd/bettong/mptable.c @@ -24,23 +24,7 @@ #include <arch/cpu.h> #include <cpu/x86/lapic.h> #include "southbridge/amd/pi/hudson/hudson.h" /* pm_ioread() */ - -u8 picr_data[0x54] = { - 0x03,0x04,0x05,0x07,0x0B,0x0A,0x1F,0x1F,0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, - 0x1F,0x1F,0x1F,0x03,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x05,0x04,0x05,0x04,0x04,0x05,0x04,0x05,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x04,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x03,0x04,0x05,0x07 -}; -u8 intr_data[0x54] = { - 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, - 0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x10,0x11,0x12,0x13 -}; +#include <southbridge/amd/common/amd_pci_util.h> static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length) { @@ -64,7 +48,6 @@ static void *smp_write_config_table(void *v) { struct mp_config_table *mc; int bus_isa; - u8 byte; /* * By the time this function gets called, the IOAPIC registers @@ -91,17 +74,6 @@ static void *smp_write_config_table(void *v) smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000); - /* PIC IRQ routine */ - for (byte = 0x0; byte < sizeof(picr_data); byte ++) { - outb(byte, 0xC00); - outb(picr_data[byte], 0xC01); - } - - /* APIC IRQ routine */ - for (byte = 0x0; byte < sizeof(intr_data); byte ++) { - outb(byte | 0x80, 0xC00); - outb(intr_data[byte], 0xC01); - } /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ @@ -115,27 +87,27 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin)) /* Internal VGA */ - PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]); + PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); + PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); /* SMBUS */ PCI_INT(0x0, 0x14, 0x0, 0x10); /* HD Audio */ - PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]); + PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]); /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); - PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]); - PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]); + PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); + PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); + PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); + PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); + PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); + PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); + PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]); /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]); - PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]); + PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]); + PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); /* on board NIC & Slot PCIE. */ |