pci configuration

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1316 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

2 files changed, 39 insertions, 0 deletions

diff --git a/src/mainboard/embeddedplanet/ep405pc/init.c b/src/mainboard/embeddedplanet/ep405pc/init.c
index 2f32203760..b7da78eba4 100644
--- a/src/mainboard/embeddedplanet/ep405pc/init.c
+++ b/src/mainboard/embeddedplanet/ep405pc/init.c
@@ -52,6 +52,11 @@ board_init(void)
 	mtebc(pb4ap, 0x04050000);
 	
 	/*
+	 * Enable PCI
+	 */
+	outb(0x80, 0xF4000001);
+
+	/*
 	 * Enable UART0
 	 */
 	outb(0x20, 0xF4000003);
diff --git a/src/mainboard/embeddedplanet/ep405pc/pci_bridge.c b/src/mainboard/embeddedplanet/ep405pc/pci_bridge.c
new file mode 100644
index 0000000000..4e67938105
--- /dev/null
+++ b/src/mainboard/embeddedplanet/ep405pc/pci_bridge.c
@@ -0,0 +1,34 @@
+/*
+ * Initialisation of the PCI bridge .
+ */
+
+#include <arch/io.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <console/console.h>
+
+static void 
+pci_bridge_init(struct device *dev)
+{
+	printk_info("Configure PCI Bridge\n");
+
+	pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY|PCI_COMMAND_MASTER);
+	pci_write_config16(dev, 0x60, 0x0f00);
+
+	printk_info("PCI Bridge configuration complete\n");
+}
+
+struct device_operations pci_bridge_ops  = {
+        .read_resources   = pci_dev_read_resources,
+        .set_resources    = pci_dev_set_resources,
+        .enable_resources = pci_dev_enable_resources,
+        .init             = pci_bridge_init,
+        .scan_bus         = 0,
+};
+
+struct pci_driver pci_bridge_pci_driver __pci_driver = {
+	/* w83c553f */
+	.ops = &pci_bridge_ops,
+	.device = PCI_DEVICE_ID_IBM_405GP,
+	.vendor = PCI_VENDOR_ID_IBM,
+};