Clean up fidvid files using indent.

Remove some special print statements.

In general, make them easier to compare.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

29 files changed, 71 insertions, 71 deletions

diff --git a/src/mainboard/amd/dbm690t/romstage.c b/src/mainboard/amd/dbm690t/romstage.c
index 676ce4ef9c..9ce0dbb7c0 100644
--- a/src/mainboard/amd/dbm690t/romstage.c
+++ b/src/mainboard/amd/dbm690t/romstage.c
@@ -18,7 +18,7 @@
  */
 
 #define RAMINIT_SYSINFO 1
-#define K8_SET_FIDVID 1
+#define SET_FIDVID 1
 #define QRANK_DIMM_SUPPORT 1
 #if CONFIG_LOGICAL_CPUS==1
 #define SET_NB_CFG_54 1
diff --git a/src/mainboard/amd/mahogany/romstage.c b/src/mainboard/amd/mahogany/romstage.c
index 97c198895d..403a795047 100644
--- a/src/mainboard/amd/mahogany/romstage.c
+++ b/src/mainboard/amd/mahogany/romstage.c
@@ -18,7 +18,7 @@
  */
 
 #define RAMINIT_SYSINFO 1
-#define K8_SET_FIDVID 1
+#define SET_FIDVID 1
 #define QRANK_DIMM_SUPPORT 1
 #if CONFIG_LOGICAL_CPUS==1
 #define SET_NB_CFG_54 1
diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c
index 3ae2d7663d..40268241a2 100644
--- a/src/mainboard/amd/mahogany_fam10/romstage.c
+++ b/src/mainboard/amd/mahogany_fam10/romstage.c
@@ -34,8 +34,8 @@
 #define FAM10_ALLOCATE_IO_RANGE 0
 
 //used by init_cpus and fidvid
-#define FAM10_SET_FIDVID 1
-#define FAM10_SET_FIDVID_CORE_RANGE 0
+#define SET_FIDVID 1
+#define SET_FIDVID_CORE_RANGE 0
 
 #include <stdint.h>
 #include <string.h>
@@ -208,7 +208,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	rs780_early_setup();
 	sb700_early_setup();
 
- #if FAM10_SET_FIDVID == 1
+ #if SET_FIDVID == 1
 	msr = rdmsr(0xc0010071);
 	printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
 
diff --git a/src/mainboard/amd/pistachio/romstage.c b/src/mainboard/amd/pistachio/romstage.c
index a3a34d6987..e84505493f 100644
--- a/src/mainboard/amd/pistachio/romstage.c
+++ b/src/mainboard/amd/pistachio/romstage.c
@@ -18,7 +18,7 @@
  */
 
 #define RAMINIT_SYSINFO 1
-#define K8_SET_FIDVID 1
+#define SET_FIDVID 1
 #define QRANK_DIMM_SUPPORT 1
 #if CONFIG_LOGICAL_CPUS==1
 #define SET_NB_CFG_54 1
diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c
index 8bc3c0aaf3..bf1d8bf4f6 100644
--- a/src/mainboard/amd/serengeti_cheetah/romstage.c
+++ b/src/mainboard/amd/serengeti_cheetah/romstage.c
@@ -10,9 +10,9 @@
 //#define K8_ALLOCATE_IO_RANGE 1
 
 //used by init_cpus and fidvid
-#define K8_SET_FIDVID 0
+#define SET_FIDVID 0
 //if we want to wait for core1 done before DQS training, set it to 0
-#define K8_SET_FIDVID_CORE0_ONLY 1
+#define SET_FIDVID_CORE0_ONLY 1
 
 #if CONFIG_K8_REV_F_SUPPORT == 1
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
@@ -164,7 +164,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
         int needs_reset;
         unsigned bsp_apicid = 0;
-#if K8_SET_FIDVID == 1
+#if SET_FIDVID == 1
 	struct cpuid_result cpuid1;
 #endif
 
@@ -228,7 +228,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 #endif
 
-#if K8_SET_FIDVID == 1
+#if SET_FIDVID == 1
 	/* Check to see if processor is capable of changing FIDVID  */
 	/* otherwise it will throw a GP# when reading FIDVID_STATUS */
 	cpuid1 = cpuid(0x80000007);
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
index d7b6c63c0e..495f3a8582 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
@@ -34,8 +34,8 @@
 #define FAM10_ALLOCATE_IO_RANGE 0
 
 //used by init_cpus and fidvid
-#define FAM10_SET_FIDVID 1
-#define FAM10_SET_FIDVID_CORE_RANGE 0
+#define SET_FIDVID 1
+#define SET_FIDVID_CORE_RANGE 0
 
 #include <stdint.h>
 #include <string.h>
@@ -211,7 +211,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	post_code(0x38);
 
- #if FAM10_SET_FIDVID == 1
+ #if SET_FIDVID == 1
 	msr = rdmsr(0xc0010071);
 	printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
 
diff --git a/src/mainboard/asrock/939a785gmh/romstage.c b/src/mainboard/asrock/939a785gmh/romstage.c
index 593e96cb90..a1a0731ff8 100644
--- a/src/mainboard/asrock/939a785gmh/romstage.c
+++ b/src/mainboard/asrock/939a785gmh/romstage.c
@@ -19,7 +19,7 @@
  */
 
 #define RAMINIT_SYSINFO 1
-#define K8_SET_FIDVID 1
+#define SET_FIDVID 1
 #define QRANK_DIMM_SUPPORT 1
 #if CONFIG_LOGICAL_CPUS==1
 #define SET_NB_CFG_54 1
diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c
index 320f23682c..a2f01b6c52 100644
--- a/src/mainboard/asus/a8v-e_se/romstage.c
+++ b/src/mainboard/asus/a8v-e_se/romstage.c
@@ -32,10 +32,10 @@ unsigned int get_sbdn(unsigned bus);
 #define QRANK_DIMM_SUPPORT 1
 
 /* Used by init_cpus and fidvid */
-#define K8_SET_FIDVID 1
+#define SET_FIDVID 1
 
 /* If we want to wait for core1 done before DQS training, set it to 0. */
-#define K8_SET_FIDVID_CORE0_ONLY 1
+#define SET_FIDVID_CORE0_ONLY 1
 
 #include <stdint.h>
 #include <string.h>
diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c
index 4183ce9b5a..b7313aee2d 100644
--- a/src/mainboard/asus/m2v-mx_se/romstage.c
+++ b/src/mainboard/asus/m2v-mx_se/romstage.c
@@ -32,10 +32,10 @@ unsigned int get_sbdn(unsigned bus);
 #define QRANK_DIMM_SUPPORT 1
 
 /* Used by init_cpus and fidvid */
-#define K8_SET_FIDVID 1
+#define SET_FIDVID 1
 
 /* If we want to wait for core1 done before DQS training, set it to 0. */
-#define K8_SET_FIDVID_CORE0_ONLY 1
+#define SET_FIDVID_CORE0_ONLY 1
 
 #if CONFIG_K8_REV_F_SUPPORT == 1
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
index 88e8830597..5a6ef2d1cd 100644
--- a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
+++ b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
@@ -32,9 +32,9 @@
 #endif
 
 //used by init_cpus and fidvid
-#define K8_SET_FIDVID 1
+#define SET_FIDVID 1
 //if we want to wait for core1 done before DQS training, set it to 0
-#define K8_SET_FIDVID_CORE0_ONLY 1
+#define SET_FIDVID_CORE0_ONLY 1
 
 #if CONFIG_K8_REV_F_SUPPORT == 1
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
@@ -235,7 +235,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         /* it will set up chains and store link pair for optimization later */
         ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 
-#if K8_SET_FIDVID == 1
+#if SET_FIDVID == 1
 
         {
                 msr_t msr;
diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c
index 964e8048b3..26ac33b0cf 100644
--- a/src/mainboard/gigabyte/m57sli/romstage.c
+++ b/src/mainboard/gigabyte/m57sli/romstage.c
@@ -30,9 +30,9 @@
 #endif
 
 //used by init_cpus and fidvid
-#define K8_SET_FIDVID 1
+#define SET_FIDVID 1
 //if we want to wait for core1 done before DQS training, set it to 0
-#define K8_SET_FIDVID_CORE0_ONLY 1
+#define SET_FIDVID_CORE0_ONLY 1
 
 #if CONFIG_K8_REV_F_SUPPORT == 1
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
@@ -249,7 +249,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         /* it will set up chains and store link pair for optimization later */
         ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 
-#if K8_SET_FIDVID == 1
+#if SET_FIDVID == 1
 
         {
                 msr_t msr;
diff --git a/src/mainboard/hp/dl145_g3/romstage.c b/src/mainboard/hp/dl145_g3/romstage.c
index f7897db6ee..e8d8b75436 100644
--- a/src/mainboard/hp/dl145_g3/romstage.c
+++ b/src/mainboard/hp/dl145_g3/romstage.c
@@ -36,9 +36,9 @@
 #endif
 
 //used by init_cpus and fidvid
-#define K8_SET_FIDVID 1
+#define SET_FIDVID 1
 //if we want to wait for core1 done before DQS training, set it to 0
-#define K8_SET_FIDVID_CORE0_ONLY 1
+#define SET_FIDVID_CORE0_ONLY 1
 
 #if CONFIG_K8_REV_F_SUPPORT == 1
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
@@ -252,7 +252,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 	bcm5785_early_setup();
 
-#if K8_SET_FIDVID == 1
+#if SET_FIDVID == 1
 	{
 		msr_t msr;
 		msr=rdmsr(0xc0010042);
diff --git a/src/mainboard/iwill/dk8_htx/romstage.c b/src/mainboard/iwill/dk8_htx/romstage.c
index da0cc57af7..76af51a762 100644
--- a/src/mainboard/iwill/dk8_htx/romstage.c
+++ b/src/mainboard/iwill/dk8_htx/romstage.c
@@ -10,9 +10,9 @@
 //#define K8_ALLOCATE_IO_RANGE 1
 
 //used by init_cpus and fidvid
-#define K8_SET_FIDVID 0
+#define SET_FIDVID 0
 //if we want to wait for core1 done before DQS training, set it to 0
-#define K8_SET_FIDVID_CORE0_ONLY 1
+#define SET_FIDVID_CORE0_ONLY 1
 
 #if CONFIG_K8_REV_F_SUPPORT == 1
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
@@ -188,7 +188,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	/* it will set up chains and store link pair for optimization later */
         ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 
-#if K8_SET_FIDVID == 1
+#if SET_FIDVID == 1
 
         {
                 msr_t msr;
diff --git a/src/mainboard/iwill/dk8s2/romstage.c b/src/mainboard/iwill/dk8s2/romstage.c
index 537d987f6a..ea4eefafb4 100644
--- a/src/mainboard/iwill/dk8s2/romstage.c
+++ b/src/mainboard/iwill/dk8s2/romstage.c
@@ -10,9 +10,9 @@
 //#define K8_ALLOCATE_IO_RANGE 1
 
 //used by init_cpus and fidvid
-#define K8_SET_FIDVID 0
+#define SET_FIDVID 0
 //if we want to wait for core1 done before DQS training, set it to 0
-#define K8_SET_FIDVID_CORE0_ONLY 1
+#define SET_FIDVID_CORE0_ONLY 1
 
 #if CONFIG_K8_REV_F_SUPPORT == 1
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
@@ -188,7 +188,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	/* it will set up chains and store link pair for optimization later */
         ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 
-#if K8_SET_FIDVID == 1
+#if SET_FIDVID == 1
 
         {
                 msr_t msr;
diff --git a/src/mainboard/iwill/dk8x/romstage.c b/src/mainboard/iwill/dk8x/romstage.c
index 537d987f6a..ea4eefafb4 100644
--- a/src/mainboard/iwill/dk8x/romstage.c
+++ b/src/mainboard/iwill/dk8x/romstage.c
@@ -10,9 +10,9 @@
 //#define K8_ALLOCATE_IO_RANGE 1
 
 //used by init_cpus and fidvid
-#define K8_SET_FIDVID 0
+#define SET_FIDVID 0
 //if we want to wait for core1 done before DQS training, set it to 0
-#define K8_SET_FIDVID_CORE0_ONLY 1
+#define SET_FIDVID_CORE0_ONLY 1
 
 #if CONFIG_K8_REV_F_SUPPORT == 1
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
@@ -188,7 +188,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	/* it will set up chains and store link pair for optimization later */
         ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 
-#if K8_SET_FIDVID == 1
+#if SET_FIDVID == 1
 
         {
                 msr_t msr;
diff --git a/src/mainboard/kontron/kt690/romstage.c b/src/mainboard/kontron/kt690/romstage.c
index 4b82aa4d88..cc7b4ef7ff 100644
--- a/src/mainboard/kontron/kt690/romstage.c
+++ b/src/mainboard/kontron/kt690/romstage.c
@@ -19,7 +19,7 @@
  */
 
 #define RAMINIT_SYSINFO 1
-#define K8_SET_FIDVID 1
+#define SET_FIDVID 1
 #define QRANK_DIMM_SUPPORT 1
 #if CONFIG_LOGICAL_CPUS==1
 #define SET_NB_CFG_54 1
diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c
index 846091a969..799c05e3c6 100644
--- a/src/mainboard/msi/ms7260/romstage.c
+++ b/src/mainboard/msi/ms7260/romstage.c
@@ -33,10 +33,10 @@
 #endif
 
 /* Used by init_cpus and fidvid. */
-#define K8_SET_FIDVID 1
+#define SET_FIDVID 1
 
 /* If we want to wait for core1 done before DQS training, set it to 0. */
-#define K8_SET_FIDVID_CORE0_ONLY 1
+#define SET_FIDVID_CORE0_ONLY 1
 
 #if CONFIG_K8_REV_F_SUPPORT == 1
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
@@ -214,7 +214,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	/* Set up chains and store link pair for optimization later. */
 	ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */
 
-#if K8_SET_FIDVID == 1
+#if SET_FIDVID == 1
 	{
 		msr_t msr = rdmsr(0xc0010042);
 		print_debug("begin msr fid, vid ");
diff --git a/src/mainboard/msi/ms9185/romstage.c b/src/mainboard/msi/ms9185/romstage.c
index e7fb87227f..2a4564c608 100644
--- a/src/mainboard/msi/ms9185/romstage.c
+++ b/src/mainboard/msi/ms9185/romstage.c
@@ -35,9 +35,9 @@
 //#define K8_ALLOCATE_IO_RANGE 1
 
 //used by init_cpus and fidvid
-#define K8_SET_FIDVID 1
+#define SET_FIDVID 1
 //if we want to wait for core1 done before DQS training, set it to 0
-#define K8_SET_FIDVID_CORE0_ONLY 1
+#define SET_FIDVID_CORE0_ONLY 1
 
 #include <stdint.h>
 #include <string.h>
@@ -221,7 +221,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 #endif
 
-#if K8_SET_FIDVID == 1
+#if SET_FIDVID == 1
 
         {
                 msr_t msr;
diff --git a/src/mainboard/msi/ms9282/romstage.c b/src/mainboard/msi/ms9282/romstage.c
index 9e6f973c93..f3cfeecb79 100644
--- a/src/mainboard/msi/ms9282/romstage.c
+++ b/src/mainboard/msi/ms9282/romstage.c
@@ -31,9 +31,9 @@
 #define QRANK_DIMM_SUPPORT 1
 
 //used by init_cpus and fidvid
-#define K8_SET_FIDVID 1
+#define SET_FIDVID 1
 //if we want to wait for core1 done before DQS training, set it to 0
-#define K8_SET_FIDVID_CORE0_ONLY 1
+#define SET_FIDVID_CORE0_ONLY 1
 
 #include <stdint.h>
 #include <string.h>
diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c
index 622dfd1058..ba1989a92e 100644
--- a/src/mainboard/msi/ms9652_fam10/romstage.c
+++ b/src/mainboard/msi/ms9652_fam10/romstage.c
@@ -30,8 +30,8 @@
 #define SET_NB_CFG_54 1
 #endif
 
-#define FAM10_SET_FIDVID 1
-#define FAM10_SET_FIDVID_CORE_RANGE 0
+#define SET_FIDVID 1
+#define SET_FIDVID_CORE_RANGE 0
 
 #define DBGP_DEFAULT 7
 
@@ -248,7 +248,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	post_code(0x38);
 
-#if FAM10_SET_FIDVID == 1
+#if SET_FIDVID == 1
 	msr = rdmsr(0xc0010071);
 	printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
 
diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c
index 3176c38e22..f5ad637c2a 100644
--- a/src/mainboard/nvidia/l1_2pvv/romstage.c
+++ b/src/mainboard/nvidia/l1_2pvv/romstage.c
@@ -30,9 +30,9 @@
 #endif
 
 //used by init_cpus and fidvid
-#define K8_SET_FIDVID 0
+#define SET_FIDVID 0
 //if we want to wait for core1 done before DQS training, set it to 0
-#define K8_SET_FIDVID_CORE0_ONLY 1
+#define SET_FIDVID_CORE0_ONLY 1
 
 #if CONFIG_K8_REV_F_SUPPORT == 1
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
@@ -236,7 +236,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	/* it will set up chains and store link pair for optimization later */
 	ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 
-#if K8_SET_FIDVID == 1
+#if SET_FIDVID == 1
 
 	{
 		msr_t msr;
diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c
index 7f668f4c15..964f4dab67 100644
--- a/src/mainboard/supermicro/h8dme/romstage.c
+++ b/src/mainboard/supermicro/h8dme/romstage.c
@@ -27,9 +27,9 @@
 #endif
 
 // used by init_cpus and fidvid
-#define K8_SET_FIDVID 1
+#define SET_FIDVID 1
 //if we want to wait for core1 done before DQS training, set it to 0
-#define K8_SET_FIDVID_CORE0_ONLY 1
+#define SET_FIDVID_CORE0_ONLY 1
 
 #if CONFIG_K8_REV_F_SUPPORT == 1
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
@@ -295,7 +295,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	/* it will set up chains and store link pair for optimization later */
 	ht_setup_chains_x(sysinfo);	// it will init sblnk and sbbusn, nodes, sbdn
 
-#if K8_SET_FIDVID == 1
+#if SET_FIDVID == 1
 
 	{
 		msr_t msr;
diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c
index 7245b37fb2..940dea3d82 100644
--- a/src/mainboard/supermicro/h8dmr/romstage.c
+++ b/src/mainboard/supermicro/h8dmr/romstage.c
@@ -30,9 +30,9 @@
 #endif
 
 //used by init_cpus and fidvid
-#define K8_SET_FIDVID 1
+#define SET_FIDVID 1
 //if we want to wait for core1 done before DQS training, set it to 0
-#define K8_SET_FIDVID_CORE0_ONLY 1
+#define SET_FIDVID_CORE0_ONLY 1
 
 #if CONFIG_K8_REV_F_SUPPORT == 1
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
@@ -223,7 +223,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         /* it will set up chains and store link pair for optimization later */
         ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 
-#if K8_SET_FIDVID == 1
+#if SET_FIDVID == 1
 
         {
                 msr_t msr;
diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
index 095c4b1f1f..fb91d62dd1 100644
--- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
@@ -30,8 +30,8 @@
 #define SET_NB_CFG_54 1
 #endif
 
-#define FAM10_SET_FIDVID 1
-#define FAM10_SET_FIDVID_CORE_RANGE 0
+#define SET_FIDVID 1
+#define SET_FIDVID_CORE_RANGE 0
 
 #include <stdint.h>
 #include <string.h>
@@ -235,7 +235,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
  post_code(0x38);
 
-#if FAM10_SET_FIDVID == 1
+#if SET_FIDVID == 1
  msr = rdmsr(0xc0010071);
  printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
 
diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c
index 3c4dedefaf..fc32549eb5 100644
--- a/src/mainboard/supermicro/h8qme_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c
@@ -30,8 +30,8 @@
 #define SET_NB_CFG_54 1
 #endif
 
-#define FAM10_SET_FIDVID 1
-#define FAM10_SET_FIDVID_CORE_RANGE 0
+#define SET_FIDVID 1
+#define SET_FIDVID_CORE_RANGE 0
 
 #include <stdint.h>
 #include <string.h>
@@ -280,7 +280,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
  post_code(0x38);
 
-#if FAM10_SET_FIDVID == 1
+#if SET_FIDVID == 1
  msr = rdmsr(0xc0010071);
  printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
 
diff --git a/src/mainboard/technexion/tim5690/romstage.c b/src/mainboard/technexion/tim5690/romstage.c
index 2b7ede214b..f9a1054949 100644
--- a/src/mainboard/technexion/tim5690/romstage.c
+++ b/src/mainboard/technexion/tim5690/romstage.c
@@ -18,7 +18,7 @@
  */
 
 #define RAMINIT_SYSINFO 1
-#define K8_SET_FIDVID 1
+#define SET_FIDVID 1
 #define QRANK_DIMM_SUPPORT 1
 #if CONFIG_LOGICAL_CPUS==1
 #define SET_NB_CFG_54 1
diff --git a/src/mainboard/technexion/tim8690/romstage.c b/src/mainboard/technexion/tim8690/romstage.c
index 71ae749ca2..cfdddec96e 100644
--- a/src/mainboard/technexion/tim8690/romstage.c
+++ b/src/mainboard/technexion/tim8690/romstage.c
@@ -18,7 +18,7 @@
  */
 
 #define RAMINIT_SYSINFO 1
-#define K8_SET_FIDVID 1
+#define SET_FIDVID 1
 #define QRANK_DIMM_SUPPORT 1
 #if CONFIG_LOGICAL_CPUS==1
 #define SET_NB_CFG_54 1
diff --git a/src/mainboard/tyan/s2912/romstage.c b/src/mainboard/tyan/s2912/romstage.c
index 85b5321ac8..ed078397f9 100644
--- a/src/mainboard/tyan/s2912/romstage.c
+++ b/src/mainboard/tyan/s2912/romstage.c
@@ -30,9 +30,9 @@
 #endif
 
 //used by init_cpus and fidvid
-#define K8_SET_FIDVID 0
+#define SET_FIDVID 0
 //if we want to wait for core1 done before DQS training, set it to 0
-#define K8_SET_FIDVID_CORE0_ONLY 1
+#define SET_FIDVID_CORE0_ONLY 1
 
 #if CONFIG_K8_REV_F_SUPPORT == 1
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
@@ -232,7 +232,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	/* it will set up chains and store link pair for optimization later */
 	ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 
-#if K8_SET_FIDVID == 1
+#if SET_FIDVID == 1
 
 	{
 		msr_t msr;
diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c
index 5c72639d5e..54fb96ecbf 100644
--- a/src/mainboard/tyan/s2912_fam10/romstage.c
+++ b/src/mainboard/tyan/s2912_fam10/romstage.c
@@ -30,8 +30,8 @@
 #define SET_NB_CFG_54 1
 #endif
 
-#define FAM10_SET_FIDVID 1
-#define FAM10_SET_FIDVID_CORE_RANGE 0
+#define SET_FIDVID 1
+#define SET_FIDVID_CORE_RANGE 0
 
 #define DBGP_DEFAULT 7
 
@@ -243,7 +243,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	post_code(0x38);
 
-#if FAM10_SET_FIDVID == 1
+#if SET_FIDVID == 1
 	msr = rdmsr(0xc0010071);
 	printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);