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| author | Greg Watson <jarrah@users.sourceforge.net> | 2004-01-14 17:21:22 +0000 |
|---|---|---|
| committer | Greg Watson <jarrah@users.sourceforge.net> | 2004-01-14 17:21:22 +0000 |
| commit | b020d53352c1bbe1084c9c499b45cfb345fc8677 (patch) | |
| tree | 1938b5ec4d8a2e388a19b0a9b38e7497da16b9b4 /src/mainboard | |
| parent | bf5b58480129dcd6a770f3f2b237511fb295918e (diff) | |
| download | coreboot-b020d53352c1bbe1084c9c499b45cfb345fc8677.tar.xz | |
*** empty log message ***
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1335 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/embeddedplanet/ep405pc/init.c | 4 | ||||
| -rw-r--r-- | src/mainboard/motorola/sandpoint/Config.lb | 12 |
2 files changed, 9 insertions, 7 deletions
diff --git a/src/mainboard/embeddedplanet/ep405pc/init.c b/src/mainboard/embeddedplanet/ep405pc/init.c index b7da78eba4..240a392260 100644 --- a/src/mainboard/embeddedplanet/ep405pc/init.c +++ b/src/mainboard/embeddedplanet/ep405pc/init.c @@ -52,9 +52,9 @@ board_init(void) mtebc(pb4ap, 0x04050000); /* - * Enable PCI + * Enable FLASH, NVRAM, POR */ - outb(0x80, 0xF4000001); + outb(0x9C, 0xF4000002); /* * Enable UART0 diff --git a/src/mainboard/motorola/sandpoint/Config.lb b/src/mainboard/motorola/sandpoint/Config.lb index 12d840620b..53bc6a4c0e 100644 --- a/src/mainboard/motorola/sandpoint/Config.lb +++ b/src/mainboard/motorola/sandpoint/Config.lb @@ -53,11 +53,13 @@ end ## Include the secondary Configuration files ## southbridge winbond/w83c553 end -superio NSC/pc97307 - register "com1" = "{1}" - register "lpt" = "{0}" - register "port" = "TTYS0_BASE" -end + +# Already intialized in board_init() +#superio NSC/pc97307 +# register "com1" = "{1}" +# register "lpt" = "{0}" +# register "port" = "UART0_IO_BASE" +#end ## ## Build the objects we have code for in this directory. |