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| author | Duncan Laurie <dlaurie@chromium.org> | 2015-11-05 07:12:33 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-11-11 20:43:52 +0100 |
| commit | b13845191ff96dea4e88c220167fa7f3c1576d69 (patch) | |
| tree | d01544fe39811f7896112280b8a2e44bf98a8e16 /src/mainboard | |
| parent | bec1108cbc806977196e4f7c70ffa2efd349bb52 (diff) | |
| download | coreboot-b13845191ff96dea4e88c220167fa7f3c1576d69.tar.xz | |
google/chell: Fix USB port assignment again
The net names are offset by 1. My board is not stable enough
to really test all of these yet...
BUG=chrome-os-partner:46289
BRANCH=none
TEST=emerge-chell coreboot
Change-Id: I65e17323f2819eca130c1bf0ccbc3ea0ec2f383f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 327194dcfcb3a5c9f431b1a2e26c230cb2b2a48b
Original-Change-Id: I50e9ea091bb6e6a1da3a9434ae0fbf3f652fa354
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/311113
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12389
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/chell/devicetree.cb | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/mainboard/google/chell/devicetree.cb b/src/mainboard/google/chell/devicetree.cb index 05e37bfbfe..d5150688d8 100644 --- a/src/mainboard/google/chell/devicetree.cb +++ b/src/mainboard/google/chell/devicetree.cb @@ -54,11 +54,11 @@ chip soc/intel/skylake register "PcieRpClkReqNumber[4]" = "2" register "usb2_ports[0]" = "USB2_PORT_TYPE_C" # Type-C Port 1 - register "usb2_ports[2]" = "USB2_PORT_TYPE_C" # Type-C Port 2 - register "usb2_ports[3]" = "USB2_PORT_MID" # Bluetooth - register "usb2_ports[5]" = "USB2_PORT_MID" # Type-A Port - register "usb2_ports[7]" = "USB2_PORT_FLEX" # Camera - register "usb2_ports[9]" = "USB2_PORT_MID" # SD + register "usb2_ports[1]" = "USB2_PORT_TYPE_C" # Type-C Port 2 + register "usb2_ports[2]" = "USB2_PORT_MID" # Bluetooth + register "usb2_ports[4]" = "USB2_PORT_MID" # Type-A Port + register "usb2_ports[6]" = "USB2_PORT_FLEX" # Camera + register "usb2_ports[8]" = "USB2_PORT_MID" # SD register "usb3_ports[0]" = "USB3_PORT_DEFAULT" # Type-C Port 1 register "usb3_ports[1]" = "USB3_PORT_DEFAULT" # Type-C Port 2 |