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| author | John Su <john_su@compal.corp-partner.google.com> | 2019-01-10 21:52:39 +0800 |
|---|---|---|
| committer | Duncan Laurie <dlaurie@chromium.org> | 2019-01-16 21:45:51 +0000 |
| commit | cc394d4d37533a4977c1da629c8ebf405a91d32a (patch) | |
| tree | d58b1c6f936bc715d1d3fb9de87d0ab16bfb7c07 /src/mainboard | |
| parent | c3e75b42a471cc64fec37a464eef7088492ec04e (diff) | |
| download | coreboot-cc394d4d37533a4977c1da629c8ebf405a91d32a.tar.xz | |
mb/google/sarien/variants/sarien: Set up tcc offset for sarien
Change tcc offset from 15 to 3 for sarien.
BUG=b:122636962
TEST=Match the result from TAT UI
Change-Id: I1c5d144e92d1e6e9c81b3e6686805ccf744b7203
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/30808
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/sarien/variants/sarien/devicetree.cb | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 37ef3dc5e0..4334c45083 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -74,6 +74,9 @@ chip soc/intel/cannonlake #| I2C1 | Touchpad | #| I2C4 | H1 TPM | #+-------------------+---------------------------+ + + register "tcc_offset" = "3" + register "common_soc_config" = "{ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, .i2c[0] = { |