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| author | Patrick Rudolph <siro@das-labor.org> | 2018-07-14 16:46:29 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-07-16 07:44:54 +0000 |
| commit | cff16b6f9df38135ab7619b61332318dded45edc (patch) | |
| tree | f54e6df88b763cbd2d949318e22809349c7fd881 /src/mainboard | |
| parent | 50a2a868324538563e91813d6cf263f8b7da538b (diff) | |
| download | coreboot-cff16b6f9df38135ab7619b61332318dded45edc.tar.xz | |
mb/lenovo/x201: Fix EC SSDT
Move the EC under the LPC PCI device to make sure that the SSDT path
matches the DSDT. Matches the behaviour of all other Lenovo devices.
Change-Id: I9ded7f639866d71d39ea0d5d0c36602d386c177f
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/27481
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Matthias Gazzari <mail@qtux.eu>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/lenovo/x201/devicetree.cb | 84 |
1 files changed, 42 insertions, 42 deletions
diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb index a1746bdee8..fa33aeb431 100644 --- a/src/mainboard/lenovo/x201/devicetree.cb +++ b/src/mainboard/lenovo/x201/devicetree.cb @@ -36,48 +36,6 @@ chip northbridge/intel/nehalem register "gfx.use_spread_spectrum_clock" = "1" register "gfx.link_frequency_270_mhz" = "1" - chip ec/lenovo/pmh7 - device pnp ff.1 on # dummy - end - register "backlight_enable" = "0x01" - register "dock_event_enable" = "0x01" - end - - chip ec/lenovo/h8 - device pnp ff.2 on # dummy - io 0x60 = 0x62 - io 0x62 = 0x66 - io 0x64 = 0x1600 - io 0x66 = 0x1604 - end - - register "config0" = "0xa6" - register "config1" = "0x05" - register "config2" = "0xa0" - register "config3" = "0x01" - - register "beepmask0" = "0xfe" - register "beepmask1" = "0x96" - register "has_power_management_beeps" = "1" - - register "event2_enable" = "0xff" - register "event3_enable" = "0xff" - register "event4_enable" = "0xf4" - register "event5_enable" = "0x3c" - register "event6_enable" = "0x80" - register "event7_enable" = "0x01" - register "event8_enable" = "0x01" - register "event9_enable" = "0xff" - register "eventa_enable" = "0xff" - register "eventb_enable" = "0xff" - register "eventc_enable" = "0xff" - register "eventd_enable" = "0xff" - - register "has_bdc_detection" = "1" - register "bdc_gpio_num" = "48" - register "bdc_gpio_lvl" = "0" - end - device cpu_cluster 0 on chip cpu/intel/model_2065x device lapic 0 on end @@ -159,6 +117,48 @@ chip northbridge/intel/nehalem chip drivers/pc80/tpm device pnp 0c31.0 on end end + + chip ec/lenovo/pmh7 + device pnp ff.1 on # dummy + end + register "backlight_enable" = "0x01" + register "dock_event_enable" = "0x01" + end + + chip ec/lenovo/h8 + device pnp ff.2 on # dummy + io 0x60 = 0x62 + io 0x62 = 0x66 + io 0x64 = 0x1600 + io 0x66 = 0x1604 + end + + register "config0" = "0xa6" + register "config1" = "0x05" + register "config2" = "0xa0" + register "config3" = "0x01" + + register "beepmask0" = "0xfe" + register "beepmask1" = "0x96" + register "has_power_management_beeps" = "1" + + register "event2_enable" = "0xff" + register "event3_enable" = "0xff" + register "event4_enable" = "0xf4" + register "event5_enable" = "0x3c" + register "event6_enable" = "0x80" + register "event7_enable" = "0x01" + register "event8_enable" = "0x01" + register "event9_enable" = "0xff" + register "eventa_enable" = "0xff" + register "eventb_enable" = "0xff" + register "eventc_enable" = "0xff" + register "eventd_enable" = "0xff" + + register "has_bdc_detection" = "1" + register "bdc_gpio_num" = "48" + register "bdc_gpio_lvl" = "0" + end end device pci 1f.2 on # IDE/SATA subsystemid 0x17aa 0x2168 |