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authorCasper Chang <casper_chang@wistron.corp-partner.google.com>2019-01-22 14:44:36 +0800
committerPatrick Georgi <pgeorgi@google.com>2019-01-23 14:54:16 +0000
commitdfb5a58d8ef26a4cd7473a2e79aa5251011fdfa5 (patch)
tree4cf83c5d9cdb70c4a6693c56f948d5f0d0a18d93 /src/mainboard
parent77bcc929363a8c2e3e3aca6626a97af54e87fcf5 (diff)
downloadcoreboot-dfb5a58d8ef26a4cd7473a2e79aa5251011fdfa5.tar.xz
mb/google/arcada: Add settings for noise mitgation
Enable acoustic noise mitgation for arcada platform, the slow slew rates are fast time dived by 2. BUG=none BRANCH=none TEST=none Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: Ia838818a76a7f638b24146f3eb48493a4091c9cb Reviewed-on: https://review.coreboot.org/c/coreboot/+/31034 Reviewed-on: https://review.coreboot.org/c/31034 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/sarien/variants/arcada/devicetree.cb5
1 files changed, 5 insertions, 0 deletions
diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
index ff26cbf49f..af8fe187f3 100644
--- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
@@ -36,6 +36,11 @@ chip soc/intel/cannonlake
register "tdp_pl1_override" = "25"
register "tdp_pl2_override" = "51"
register "Device4Enable" = "1"
+ register "AcousticNoiseMitigation" = "1"
+ register "SlowSlewRateForIa" = "0"
+ register "SlowSlewRateForGt" = "0"
+ register "SlowSlewRateForSa" = "0"
+ register "SlowSlewRateForFivr" = "0"
# Intel Common SoC Config
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Left Type-C Port