diff options
| author | Peter Lemenkov <lemenkov@gmail.com> | 2018-10-23 11:17:32 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-01-14 11:57:06 +0000 |
| commit | e23245517bed9befc41bbc8c571e05782a95d5fe (patch) | |
| tree | 88bcdbc2a0da58c4f8a19335b0590948bc83cfdf /src/mainboard | |
| parent | 7b42811fa55bb5ea67c8dc71cd9436cd8ddd83c3 (diff) | |
| download | coreboot-e23245517bed9befc41bbc8c571e05782a95d5fe.tar.xz | |
mb/lenovo/*/romstage: Use macros instead of magic numbers
Apparently coreboot still uses magic numbers instead of macros in some
Lenovo mainboards. Let's use macros instead.
Note that IOTR[0123] is a 64-bit width variable.
Change-Id: Icf185c77ede5a258fe37be9e772be6804d014b57
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/29208
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/lenovo/t60/romstage.c | 12 | ||||
| -rw-r--r-- | src/mainboard/lenovo/x60/romstage.c | 12 | ||||
| -rw-r--r-- | src/mainboard/lenovo/z61t/romstage.c | 4 |
3 files changed, 14 insertions, 14 deletions
diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index 9216848f06..72dd8b42c3 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -74,8 +74,8 @@ static void early_superio_config(void) static void rcba_config(void) { /* Set up virtual channel 0 */ - RCBA32(0x0014) = 0x80000001; - RCBA32(0x001c) = 0x03128010; + RCBA32(V0CTL) = 0x80000001; + RCBA32(V1CAP) = 0x03128010; /* Device 1f interrupt pin register */ RCBA32(D31IP) = 0x00001230; @@ -100,12 +100,12 @@ static void rcba_config(void) RCBA32(FD) |= FD_INTLAN; /* Set up I/O Trap #0 for 0xfe00 (SMIC) */ - RCBA32(0x1e84) = 0x00020001; - RCBA32(0x1e80) = 0x0000fe01; + RCBA32(IOTR0) = 0x0000fe01; + RCBA32(IOTR0+4) = 0x00020001; /* Set up I/O Trap #3 for 0x800-0x80c (Trap) */ - RCBA32(0x1e9c) = 0x000200f0; - RCBA32(0x1e98) = 0x000c0801; + RCBA32(IOTR3) = 0x000c0801; + RCBA32(IOTR3+4) = 0x000200f0; } static void early_ich7_init(void) diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index 7b75d16444..8943f975af 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -73,8 +73,8 @@ static void early_superio_config(void) static void rcba_config(void) { /* Set up virtual channel 0 */ - RCBA32(0x0014) = 0x80000001; - RCBA32(0x001c) = 0x03128010; + RCBA32(V0CTL) = 0x80000001; + RCBA32(V1CAP) = 0x03128010; /* Device 1f interrupt pin register */ RCBA32(D31IP) = 0x00001230; @@ -99,12 +99,12 @@ static void rcba_config(void) RCBA32(FD) |= FD_INTLAN; /* Set up I/O Trap #0 for 0xfe00 (SMIC) */ - RCBA32(0x1e84) = 0x00020001; - RCBA32(0x1e80) = 0x0000fe01; + RCBA32(IOTR0) = 0x0000fe01; + RCBA32(IOTR0+4) = 0x00020001; /* Set up I/O Trap #3 for 0x800-0x80c (Trap) */ - RCBA32(0x1e9c) = 0x000200f0; - RCBA32(0x1e98) = 0x000c0801; + RCBA32(IOTR3) = 0x000c0801; + RCBA32(IOTR3+4) = 0x000200f0; } static void early_ich7_init(void) diff --git a/src/mainboard/lenovo/z61t/romstage.c b/src/mainboard/lenovo/z61t/romstage.c index 985cebaa87..966d0e5759 100644 --- a/src/mainboard/lenovo/z61t/romstage.c +++ b/src/mainboard/lenovo/z61t/romstage.c @@ -100,12 +100,12 @@ static void rcba_config(void) RCBA32(FD) |= FD_INTLAN; /* Set up I/O Trap #0 for 0xfe00 (SMIC) */ - RCBA32(0x1e84) = 0x00020001; RCBA32(IOTR0) = 0x0000fe01; + RCBA32(IOTR0+4) = 0x00020001; /* Set up I/O Trap #3 for 0x800-0x80c (Trap) */ - RCBA32(0x1e9c) = 0x000200f0; RCBA32(IOTR3) = 0x000c0801; + RCBA32(IOTR3+4) = 0x000200f0; } static void early_ich7_init(void) |