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authorEdwin Beasant <edwin_beasant@virtensys.com>2010-06-10 15:24:57 +0000
committerEdwin Beasant <edwin_beasant@virtensys.com>2010-06-10 15:24:57 +0000
commitf333ba09580c00a6f27e3ee0796431f5df936ecf (patch)
treed9d961b45e248d59bf8e3e582b1619887d1921b9 /src/mainboard
parent1965a237124cc8e988cf760eb7e9a61efb2adabb (diff)
downloadcoreboot-f333ba09580c00a6f27e3ee0796431f5df936ecf.tar.xz
This commit updates the Geode LX GLCP delay control setup from the v2 way to the v3 way.
This resolves problems with terminated DRAM modules. Signed-off-by: Edwin Beasant <edwin_beasant@virtensys.com> Acked-by: Roland G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5629 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/amd/db800/romstage.c6
-rw-r--r--src/mainboard/amd/norwich/romstage.c3
-rw-r--r--src/mainboard/artecgroup/dbe61/romstage.c2
-rw-r--r--src/mainboard/digitallogic/msm800sev/romstage.c3
-rw-r--r--src/mainboard/iei/pcisa-lx-800-r10/romstage.c3
-rw-r--r--src/mainboard/lippert/roadrunner-lx/romstage.c2
-rw-r--r--src/mainboard/lippert/spacerunner-lx/romstage.c2
-rw-r--r--src/mainboard/pcengines/alix1c/romstage.c3
-rw-r--r--src/mainboard/traverse/geos/romstage.c2
-rw-r--r--src/mainboard/winent/pl6064/romstage.c2
10 files changed, 16 insertions, 12 deletions
diff --git a/src/mainboard/amd/db800/romstage.c b/src/mainboard/amd/db800/romstage.c
index 893e73dd4a..48b3ede433 100644
--- a/src/mainboard/amd/db800/romstage.c
+++ b/src/mainboard/amd/db800/romstage.c
@@ -44,8 +44,8 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
}
#define ManualConf 0 /* Do automatic strapped PLL config */
-#define PLLMSRhi 0x00001490 /* Manual settings for the PLL */
-#define PLLMSRlo 0x02000030
+#define PLLMSRhi 0x000005DD /* Manual settings for the PLL */
+#define PLLMSRlo 0x00DE60EE
#define DIMM0 0xA0
#define DIMM1 0xA2
@@ -88,7 +88,7 @@ void main(unsigned long bist)
pll_reset(ManualConf);
- cpuRegInit();
+ cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
sdram_initialize(1, memctrl);
diff --git a/src/mainboard/amd/norwich/romstage.c b/src/mainboard/amd/norwich/romstage.c
index 1cc020fd41..ff6621964f 100644
--- a/src/mainboard/amd/norwich/romstage.c
+++ b/src/mainboard/amd/norwich/romstage.c
@@ -19,6 +19,7 @@
*/
#include <stdint.h>
+#include <stdlib.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
@@ -88,7 +89,7 @@ void main(unsigned long bist)
pll_reset(ManualConf);
- cpuRegInit();
+ cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
sdram_initialize(1, memctrl);
diff --git a/src/mainboard/artecgroup/dbe61/romstage.c b/src/mainboard/artecgroup/dbe61/romstage.c
index 48be6820c7..4e9c9788f7 100644
--- a/src/mainboard/artecgroup/dbe61/romstage.c
+++ b/src/mainboard/artecgroup/dbe61/romstage.c
@@ -109,7 +109,7 @@ void main(unsigned long bist)
pll_reset(ManualConf);
- cpuRegInit();
+ cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
sdram_initialize(1, memctrl);
diff --git a/src/mainboard/digitallogic/msm800sev/romstage.c b/src/mainboard/digitallogic/msm800sev/romstage.c
index 0a9b6dfe98..07c4c4d438 100644
--- a/src/mainboard/digitallogic/msm800sev/romstage.c
+++ b/src/mainboard/digitallogic/msm800sev/romstage.c
@@ -1,4 +1,5 @@
#include <stdint.h>
+#include <stdlib.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
@@ -69,7 +70,7 @@ void main(unsigned long bist)
pll_reset(ManualConf);
- cpuRegInit();
+ cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
sdram_initialize(1, memctrl);
diff --git a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c
index b41b82ba7c..35d16eaac2 100644
--- a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c
+++ b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c
@@ -19,6 +19,7 @@
*/
#include <stdint.h>
+#include <stdlib.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
@@ -92,7 +93,7 @@ void main(unsigned long bist)
pll_reset(ManualConf);
- cpuRegInit();
+ cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
sdram_initialize(1, memctrl);
diff --git a/src/mainboard/lippert/roadrunner-lx/romstage.c b/src/mainboard/lippert/roadrunner-lx/romstage.c
index 9123052452..767b42f2d3 100644
--- a/src/mainboard/lippert/roadrunner-lx/romstage.c
+++ b/src/mainboard/lippert/roadrunner-lx/romstage.c
@@ -122,7 +122,7 @@ void main(unsigned long bist)
pll_reset(ManualConf);
- cpuRegInit();
+ cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
sdram_initialize(1, memctrl);
diff --git a/src/mainboard/lippert/spacerunner-lx/romstage.c b/src/mainboard/lippert/spacerunner-lx/romstage.c
index b9b0e4f048..a62ad91c0e 100644
--- a/src/mainboard/lippert/spacerunner-lx/romstage.c
+++ b/src/mainboard/lippert/spacerunner-lx/romstage.c
@@ -184,7 +184,7 @@ void main(unsigned long bist)
pll_reset(ManualConf);
- cpuRegInit();
+ cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
/* bit1 = on-board IDE is slave, bit0 = Spread Spectrum */
if ((err = smc_send_config(SMC_CONFIG))) {
diff --git a/src/mainboard/pcengines/alix1c/romstage.c b/src/mainboard/pcengines/alix1c/romstage.c
index ee101b944f..6ec9557aac 100644
--- a/src/mainboard/pcengines/alix1c/romstage.c
+++ b/src/mainboard/pcengines/alix1c/romstage.c
@@ -18,6 +18,7 @@
*/
#include <stdint.h>
+#include <stdlib.h>
#include <spd.h>
#include <device/pci_def.h>
#include <arch/io.h>
@@ -148,7 +149,7 @@ void main(unsigned long bist)
pll_reset(ManualConf);
- cpuRegInit();
+ cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
sdram_initialize(1, memctrl);
diff --git a/src/mainboard/traverse/geos/romstage.c b/src/mainboard/traverse/geos/romstage.c
index 40501a95e0..cfdbde9b1f 100644
--- a/src/mainboard/traverse/geos/romstage.c
+++ b/src/mainboard/traverse/geos/romstage.c
@@ -88,7 +88,7 @@ void main(unsigned long bist)
pll_reset(ManualConf);
- cpuRegInit();
+ cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
sdram_initialize(1, memctrl);
diff --git a/src/mainboard/winent/pl6064/romstage.c b/src/mainboard/winent/pl6064/romstage.c
index f6d969681f..12945e3fdd 100644
--- a/src/mainboard/winent/pl6064/romstage.c
+++ b/src/mainboard/winent/pl6064/romstage.c
@@ -90,7 +90,7 @@ void main(unsigned long bist)
pll_reset(ManualConf);
- cpuRegInit();
+ cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
sdram_initialize(1, memctrl);