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authorCasper Chang <casper_chang@wistron.corp-partner.google.com>2019-01-28 21:29:01 +0800
committerPatrick Georgi <pgeorgi@google.com>2019-01-30 11:03:02 +0000
commit168f046d71ae8ec3ffc2c180a71ba2fde852f1e2 (patch)
tree0a8201c1475f34435cff0a1c0e4f960086094b90 /src/mainboard
parent76c7688f63920f0452c2c039bd152e484ab1cc67 (diff)
downloadcoreboot-168f046d71ae8ec3ffc2c180a71ba2fde852f1e2.tar.xz
mb/google/sarien/variants/arcada: Adjust TP/TS/H1 I2C CLK to meet spec
After adjustment on Arcada EVT TouchScreen: 390 KHz TouchPad: 389 KHz H1: 389 KHz BUG=b:120584026, b:120584561 BRANCH=master TEST=emerge-sarien coreboot chromeos-bootimage measure by scope Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: Ia6eb332e7a664b211a5025ad07e0d01bf7f8d5bb Reviewed-on: https://review.coreboot.org/c/31124 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/sarien/variants/arcada/devicetree.cb10
1 files changed, 6 insertions, 4 deletions
diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
index 2b0408e217..f9d458208d 100644
--- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
@@ -77,17 +77,19 @@ chip soc/intel/cannonlake
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
.i2c[0] = {
.speed = I2C_SPEED_FAST,
+ .rise_time_ns = 52,
+ .fall_time_ns = 110,
},
.i2c[1] = {
.speed = I2C_SPEED_FAST,
- .rise_time_ns = 176,
- .fall_time_ns = 15,
+ .rise_time_ns = 52,
+ .fall_time_ns = 110,
},
.i2c[4] = {
.early_init = 1,
.speed = I2C_SPEED_FAST,
- .rise_time_ns = 452,
- .fall_time_ns = 110,
+ .rise_time_ns = 36,
+ .fall_time_ns = 99,
},
}"