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authorZhao, Lijian <lijian.zhao@intel.com>2016-05-17 19:26:18 -0700
committerAaron Durbin <adurbin@chromium.org>2016-06-09 20:23:50 +0200
commit1a718642ead0aa42561e4db30431066d53fdb57c (patch)
tree0b9983098923cd251c0762ca365e81d0051f0ce2 /src/mainboard
parent1b8ee0b88a2d3be79642aff390f3bcc98ad22036 (diff)
downloadcoreboot-1a718642ead0aa42561e4db30431066d53fdb57c.tar.xz
intel/amenia: Program EMMC dll setting
EMMC TX DATA Control needs to be programmed to 0x1A1A to make amenia system can run stable on EMMC with HS400 mode. Change-Id: I42c23ff7e6956e75de5e1b1339a570b35d999301 Signed-off-by: Zhao, Lijian <lijian.zhao@intel.com> Tested-by: Petrov, Andrey <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15092 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/intel/amenia/devicetree.cb5
1 files changed, 5 insertions, 0 deletions
diff --git a/src/mainboard/intel/amenia/devicetree.cb b/src/mainboard/intel/amenia/devicetree.cb
index af06848a84..8128c713ee 100644
--- a/src/mainboard/intel/amenia/devicetree.cb
+++ b/src/mainboard/intel/amenia/devicetree.cb
@@ -10,6 +10,11 @@ chip soc/intel/apollolake
# Integrated Sensor Hub
register "integrated_sensor_hub_enable" = "0"
+ # EMMC TX DATA Delay 1#
+ # 0x1A[14:8] stands for 26*125 = 3250 pSec delay for HS400
+ # 0x1A[6:0] stands for 26*125 = 3250 pSec delay for SDR104/HS200
+ register "emmc_tx_data_cntl1" = "0x1A1A" # HS400 required
+
device domain 0 on
device pci 00.0 on end # - Host Bridge
device pci 00.1 on end # - DPTF