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authorJohn Zhao <john.zhao@intel.com>2018-11-05 14:45:02 -0800
committerPatrick Georgi <pgeorgi@google.com>2018-11-08 11:32:19 +0000
commit1e6a889752b4d9c511522ccd1ae585b91e8bdf23 (patch)
tree49ccff1bd4ce7d89f74fda91af915d0b75f77aad /src/mainboard
parente673e5c09eebad3efbe19d15d064d131771abc2c (diff)
downloadcoreboot-1e6a889752b4d9c511522ccd1ae585b91e8bdf23.tar.xz
mb/google/octopus/variants/baseboard: Improve cold boot and S3 resume
FSP 2.0.7.1 provides UPD interface to execute IPC command. Configure PmicPmcIpcCtrl for PMC to program PMIC PCH_PWROK delay from default 100ms to 10ms to improve cold boot and S3 resume performance. BUG=b:118676361 CQ-DEPEND=CL:*703187 TEST=Verified system_resume_firmware_ec time reduction. Change-Id: I41b8268c752573d828e31a1d94d3f175aa3cc145 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/29485 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/octopus/variants/baseboard/devicetree.cb18
1 files changed, 18 insertions, 0 deletions
diff --git a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb
index 3d22525d4c..1119882c3f 100644
--- a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb
@@ -177,4 +177,22 @@ chip soc/intel/apollolake
end # - ESPI
device pci 1f.1 on end # - SMBUS
end
+
+ # FSP provides UPD interface to execute IPC command. PMIC has
+ # I2C_Slave_Address (31:24): 0x5E, Register_Offset (23:16): 0x43,
+ # RegOrValue (15:8): 0x2 and RegAndValue (7:0) 0xF8.
+ # The register is defined as: D[7:3] RSVD, D[2:0] PWROKDELAY.
+ # uint8 RegOrValue, RegAndValue, PmicReadReg
+ # RegOrValue = (UINT8)((PmicPmcIpcCtrl >> 8) & 0Xff);
+ # RegAndValue = (UINT8)(PmicPmcIpcCtrl & 0Xff);
+ # PmicReadReg &= RegAndValue;
+ # PmicReadReg |= RegOrValue;
+ # PmicReadReg value will be programmed into PMIC D[2:0] PWROKDELAY field
+ # and D[7:3] RSVD will not be impacted.
+
+ # Configure PmicPmcIpcCtrl for PMC to program PMIC PCH_PWROK delay
+ # from 100ms to 10ms.
+ # PWROKDELAY[2:0]: 000=2.5ms, 001=5.0ms, 010=10ms, 011=15ms, 100=20ms,
+ # 101=50ms, 110=75ms, 111=100ms (default)
+ register "PmicPmcIpcCtrl" = "0x5e4302f8"
end