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| author | Aaron Durbin <adurbin@chromium.org> | 2016-11-03 08:34:23 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-11-04 23:19:10 +0100 |
| commit | 242cb3b601396a5178680f7731b8d5f9d257c646 (patch) | |
| tree | cfe84021ad5268d1e768af6b57689783979a1af2 /src/mainboard | |
| parent | 46575fb1d4f00e0d1e69e9ad38acb4c1e4b38711 (diff) | |
| download | coreboot-242cb3b601396a5178680f7731b8d5f9d257c646.tar.xz | |
reef: tune tpm i2c frequency to 400kHz
This brings the frequency down to 400kHz which is spec for
fast i2c.
BUG=chrome-os-partner:58889
Change-Id: I8689a062b5457aa431eaa7fb688a7170dad83fcf
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17214
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/reef/variants/baseboard/devicetree.cb | 14 |
1 files changed, 12 insertions, 2 deletions
diff --git a/src/mainboard/google/reef/variants/baseboard/devicetree.cb b/src/mainboard/google/reef/variants/baseboard/devicetree.cb index 30d61f63d4..559b0071be 100644 --- a/src/mainboard/google/reef/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/reef/variants/baseboard/devicetree.cb @@ -71,8 +71,18 @@ chip soc/intel/apollolake register "gpe0_dw2" = "PMC_GPE_N_63_32" register "gpe0_dw3" = "PMC_GPE_SW_31_0" - # Enable I2C2 bus early for TPM access - register "i2c[2].early_init" = "1" + # Enable I2C2 bus early for TPM access and configure as 400kHz + # with manually tuned values. + register "i2c[2]" = "{ + .early_init = 1, + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 0xd0, + .scl_hcnt = 0x68, + .sda_hold = 0x27, + } + }" # Minimum SLP S3 assertion width 28ms. register "slp_s3_assertion_width_usecs" = "28000" |