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| author | David Wu <david_wu@quanta.corp-partner.google.com> | 2020-09-08 15:30:29 +0800 |
|---|---|---|
| committer | Edward O'Callaghan <quasisec@chromium.org> | 2020-09-09 00:11:58 +0000 |
| commit | 299cb4bb8af9be08d1a5a39e23c6ff7cd96c1ad5 (patch) | |
| tree | e9323023f6790f1d900d3b86a0882a9675fe5a18 /src/mainboard | |
| parent | 8e0f9f30f666de37238fa42b1bd33f33ae99c0fb (diff) | |
| download | coreboot-299cb4bb8af9be08d1a5a39e23c6ff7cd96c1ad5.tar.xz | |
mb/google/puff: Increase DPTF parameters for faffy
Update critical and passive policy for TSR0.
BUG=b:167477885
BRANCH=puff
TEST=build and verify by thermal team
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I244e1b5cacabf5b73c47b4039ae150cd17fcd0fc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45169
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/hatch/variants/faffy/overridetree.cb | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/google/hatch/variants/faffy/overridetree.cb b/src/mainboard/google/hatch/variants/faffy/overridetree.cb index c1bd1e4485..a05cb9d986 100644 --- a/src/mainboard/google/hatch/variants/faffy/overridetree.cb +++ b/src/mainboard/google/hatch/variants/faffy/overridetree.cb @@ -281,11 +281,11 @@ chip soc/intel/cannonlake chip drivers/intel/dptf ## Passive Policy register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 5000)" - register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 63, 5000)" + register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000)" ## Critical Policy register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 100, SHUTDOWN)" - register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 78, SHUTDOWN)" + register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN)" ## Power Limits Control # 10-15W PL1 in 200mW increments, avg over 28-32s interval |