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| author | Peter Lemenkov <lemenkov@gmail.com> | 2019-11-27 15:07:31 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-12-06 15:21:38 +0000 |
| commit | 2ee6fbf0d7593f0c78677c9c2bb307e47cea6c23 (patch) | |
| tree | 93c5d069c16cf6cd0a5b50d7bf020a6c1a3034e2 /src/mainboard | |
| parent | 67910db907fb3d5feacdbfaa40952a88f673795a (diff) | |
| download | coreboot-2ee6fbf0d7593f0c78677c9c2bb307e47cea6c23.tar.xz | |
mb/lenovo/t520/devicetree: Use subsystemid inheritance
Change-Id: Iffeb634c73f58aa1cddac5210d75fda75a3d5e92
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37293
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/lenovo/t520/variants/t520/devicetree.cb | 13 |
1 files changed, 9 insertions, 4 deletions
diff --git a/src/mainboard/lenovo/t520/variants/t520/devicetree.cb b/src/mainboard/lenovo/t520/variants/t520/devicetree.cb index 7893daf9ec..0bfa18f4a6 100644 --- a/src/mainboard/lenovo/t520/variants/t520/devicetree.cb +++ b/src/mainboard/lenovo/t520/variants/t520/devicetree.cb @@ -37,9 +37,13 @@ chip northbridge/intel/sandybridge register "pci_mmio_size" = "2048" device domain 0 on + subsystemid 0x17aa 0x21cf inherit + device pci 00.0 on end # host bridge device pci 01.0 on end # NVIDIA Corporation GF119M [NVS 4200M] - device pci 02.0 on end # vga controller + device pci 02.0 on + subsystemid 0x17aa 0x21d1 + end # vga controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH # GPI routing @@ -73,7 +77,9 @@ chip northbridge/intel/sandybridge device pci 16.1 off end device pci 16.2 off end device pci 16.3 off end - device pci 19.0 on end # Intel Gigabit Ethernet + device pci 19.0 on # Intel Gigabit Ethernet + subsystemid 0x17aa 0x21ce + end device pci 1a.0 on end # USB2 EHCI #2 device pci 1b.0 on end # High Definition Audio device pci 1c.0 off end # PCIe Port #1 @@ -91,8 +97,7 @@ chip northbridge/intel/sandybridge device pci 1f.0 on #LPC bridge chip ec/lenovo/pmh7 - device pnp ff.1 on # dummy - end + device pnp ff.1 on end # dummy register "backlight_enable" = "0x01" register "dock_event_enable" = "0x01" end |