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authorOskar Enoksson <oskeno@foi.se>2010-08-20 20:37:27 +0000
committerMyles Watson <mylesgw@gmail.com>2010-08-20 20:37:27 +0000
commit37106a762a2158003c6267873fd6ebc1ec5d685e (patch)
tree07e0b3dfb9439337cca471376a86e87068f195c7 /src/mainboard
parentca1a76247920ae3953db12ec290cf702053e970a (diff)
downloadcoreboot-37106a762a2158003c6267873fd6ebc1ec5d685e.tar.xz
Add support for the HP DL145 G1, based on the Tyan s2881.
Signed-off-by: Oskar Enoksson <oskeno@foi.se> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5723 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/hp/Kconfig1
-rw-r--r--src/mainboard/hp/dl145_g1/Kconfig81
-rw-r--r--src/mainboard/hp/dl145_g1/Makefile.inc1
-rw-r--r--src/mainboard/hp/dl145_g1/chip.h6
-rw-r--r--src/mainboard/hp/dl145_g1/cmos.layout98
-rw-r--r--src/mainboard/hp/dl145_g1/devicetree.cb158
-rw-r--r--src/mainboard/hp/dl145_g1/get_bus_conf.c128
-rw-r--r--src/mainboard/hp/dl145_g1/irq_tables.c107
-rw-r--r--src/mainboard/hp/dl145_g1/mainboard.c29
-rw-r--r--src/mainboard/hp/dl145_g1/mptable.c132
-rw-r--r--src/mainboard/hp/dl145_g1/resourcemap.c266
-rw-r--r--src/mainboard/hp/dl145_g1/romstage.c207
12 files changed, 1214 insertions, 0 deletions
diff --git a/src/mainboard/hp/Kconfig b/src/mainboard/hp/Kconfig
index 36857e5f87..751cdc0473 100644
--- a/src/mainboard/hp/Kconfig
+++ b/src/mainboard/hp/Kconfig
@@ -2,6 +2,7 @@ choice
prompt "Mainboard model"
depends on VENDOR_HP
+source "src/mainboard/hp/dl145_g1/Kconfig"
source "src/mainboard/hp/dl145_g3/Kconfig"
source "src/mainboard/hp/e_vectra_p2706t/Kconfig"
diff --git a/src/mainboard/hp/dl145_g1/Kconfig b/src/mainboard/hp/dl145_g1/Kconfig
new file mode 100644
index 0000000000..a6e8de9b84
--- /dev/null
+++ b/src/mainboard/hp/dl145_g1/Kconfig
@@ -0,0 +1,81 @@
+config BOARD_HP_DL145_G1
+ bool "ProLiant DL145 G1"
+ select ARCH_X86
+ select CPU_AMD_SOCKET_940
+ select NORTHBRIDGE_AMD_AMDK8
+ select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
+ select SOUTHBRIDGE_AMD_AMD8131
+ select SOUTHBRIDGE_AMD_AMD8111
+ select SUPERIO_WINBOND_W83627HF
+ select HAVE_BUS_CONFIG
+ select HAVE_HARD_RESET
+ select HAVE_OPTION_TABLE
+ select HAVE_PIRQ_TABLE
+ select HAVE_MP_TABLE
+ select BOARD_ROMSIZE_KB_512
+# select SB_HT_CHAIN_UNITID_OFFSET_ONLY
+
+config MAINBOARD_DIR
+ string
+ default hp/dl145_g1
+ depends on BOARD_HP_DL145_G1
+
+config APIC_ID_OFFSET
+ hex
+ default 0x0
+ depends on BOARD_HP_DL145_G1
+
+config SB_HT_CHAIN_ON_BUS0
+ int
+ default 2
+ depends on BOARD_HP_DL145_G1
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "ProLiant DL145 G1"
+ depends on BOARD_HP_DL145_G1
+
+config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+ hex
+ default 0x1022
+ depends on BOARD_HP_DL145_G1
+
+config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+ hex
+ default 0x7460
+ depends on BOARD_HP_DL145_G1
+
+config HW_MEM_HOLE_SIZEK
+ hex
+ default 0x100000
+ depends on BOARD_HP_DL145_G1
+
+config MAX_CPUS
+ int
+ default 4
+ depends on BOARD_HP_DL145_G1
+
+config MAX_PHYSICAL_CPUS
+ int
+ default 2
+ depends on BOARD_HP_DL145_G1
+
+config HW_MEM_HOLE_SIZE_AUTO_INC
+ bool
+ default n
+ depends on BOARD_HP_DL145_G1
+
+config HT_CHAIN_UNITID_BASE
+ hex
+ default 0x1
+ depends on BOARD_HP_DL145_G1
+
+config HT_CHAIN_END_UNITID_BASE
+ hex
+ default 0x6
+ depends on BOARD_HP_DL145_G1
+
+config IRQ_SLOT_COUNT
+ int
+ default 9
+ depends on BOARD_HP_DL145_G1
diff --git a/src/mainboard/hp/dl145_g1/Makefile.inc b/src/mainboard/hp/dl145_g1/Makefile.inc
new file mode 100644
index 0000000000..f3c44cf415
--- /dev/null
+++ b/src/mainboard/hp/dl145_g1/Makefile.inc
@@ -0,0 +1 @@
+obj-y += ../../../drivers/i2c/i2cmux/i2cmux.o \ No newline at end of file
diff --git a/src/mainboard/hp/dl145_g1/chip.h b/src/mainboard/hp/dl145_g1/chip.h
new file mode 100644
index 0000000000..49842a07d3
--- /dev/null
+++ b/src/mainboard/hp/dl145_g1/chip.h
@@ -0,0 +1,6 @@
+extern struct chip_operations mainboard_ops;
+
+struct mainboard_config {
+ int fixup_scsi;
+ int fixup_vga;
+};
diff --git a/src/mainboard/hp/dl145_g1/cmos.layout b/src/mainboard/hp/dl145_g1/cmos.layout
new file mode 100644
index 0000000000..924934c137
--- /dev/null
+++ b/src/mainboard/hp/dl145_g1/cmos.layout
@@ -0,0 +1,98 @@
+entries
+
+#start-bit length config config-ID name
+#0 8 r 0 seconds
+#8 8 r 0 alarm_seconds
+#16 8 r 0 minutes
+#24 8 r 0 alarm_minutes
+#32 8 r 0 hours
+#40 8 r 0 alarm_hours
+#48 8 r 0 day_of_week
+#56 8 r 0 day_of_month
+#64 8 r 0 month
+#72 8 r 0 year
+#80 4 r 0 rate_select
+#84 3 r 0 REF_Clock
+#87 1 r 0 UIP
+#88 1 r 0 auto_switch_DST
+#89 1 r 0 24_hour_mode
+#90 1 r 0 binary_values_enable
+#91 1 r 0 square-wave_out_enable
+#92 1 r 0 update_finished_enable
+#93 1 r 0 alarm_interrupt_enable
+#94 1 r 0 periodic_interrupt_enable
+#95 1 r 0 disable_clock_updates
+#96 288 r 0 temporary_filler
+0 384 r 0 reserved_memory
+384 1 e 4 boot_option
+385 1 e 4 last_boot
+386 1 e 1 ECC_memory
+388 4 r 0 reboot_bits
+392 3 e 5 baud_rate
+395 1 e 1 hw_scrubber
+396 1 e 1 interleave_chip_selects
+397 2 e 8 max_mem_clock
+399 1 e 2 multi_core
+400 1 e 1 power_on_after_fail
+412 4 e 6 debug_level
+416 4 e 7 boot_first
+420 4 e 7 boot_second
+424 4 e 7 boot_third
+428 4 h 0 boot_index
+432 8 h 0 boot_countdown
+440 4 e 9 slow_cpu
+444 1 e 1 nmi
+445 1 e 1 iommu
+728 256 h 0 user_data
+984 16 h 0 check_sum
+# Reserve the extended AMD configuration registers
+1000 24 r 0 amd_reserved
+
+
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+5 0 115200
+5 1 57600
+5 2 38400
+5 3 19200
+5 4 9600
+5 5 4800
+5 6 2400
+5 7 1200
+6 6 Notice
+6 7 Info
+6 8 Debug
+6 9 Spew
+7 0 Network
+7 1 HDD
+7 2 Floppy
+7 8 Fallback_Network
+7 9 Fallback_HDD
+7 10 Fallback_Floppy
+#7 3 ROM
+8 0 DDR400
+8 1 DDR333
+8 2 DDR266
+8 3 DDR200
+9 0 off
+9 1 87.5%
+9 2 75.0%
+9 3 62.5%
+9 4 50.0%
+9 5 37.5%
+9 6 25.0%
+9 7 12.5%
+
+checksums
+
+checksum 392 983 984
+
+
diff --git a/src/mainboard/hp/dl145_g1/devicetree.cb b/src/mainboard/hp/dl145_g1/devicetree.cb
new file mode 100644
index 0000000000..bd37862bcf
--- /dev/null
+++ b/src/mainboard/hp/dl145_g1/devicetree.cb
@@ -0,0 +1,158 @@
+chip northbridge/amd/amdk8/root_complex
+ device lapic_cluster 0 on
+ chip cpu/amd/socket_940
+ device lapic 0 on end
+ end
+ end
+ device pci_domain 0 on
+ chip northbridge/amd/amdk8
+ device pci 18.0 on end # link 0
+ device pci 18.0 on end # link 1
+ device pci 18.0 on # link 2
+ chip southbridge/amd/amd8131
+ # the on/off keyword is mandatory
+ device pci 0.0 on end
+ device pci 0.1 on end
+ device pci 1.0 on end
+ device pci 1.1 on end
+ device pci 2.0 on end
+ device pci 2.1 on end
+ device pci 3.0 off end
+ end
+ chip southbridge/amd/amd8111
+ # this "device pci 0.0" is the parent the next one
+ # PCI bridge
+ device pci 0.0 on
+ device pci 0.0 on end # LPC
+ device pci 0.1 on end # IDE
+ device pci 0.2 on end # SMbus
+ device pci 0.3 on end # ACPI
+ device pci 1.0 off end
+ #device pci 5.0 on end # SiI
+ #device pci 6.0 on end
+ end
+ device pci 1.0 on
+ chip superio/winbond/w83627hf
+ device pnp 2e.0 off # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 off # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ drq 0x74 = 1
+ end
+ device pnp 2e.2 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 on # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.5 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ irq 0x72 = 12
+ end
+ device pnp 2e.6 off # CIR
+ end
+ device pnp 2e.7 off # GAM_MIDI_GIPO1
+ io 0x60 = 0x201
+ io 0x62 = 0x330
+ irq 0x70 = 9
+ end
+ device pnp 2e.8 on # GPIO2
+ end
+ device pnp 2e.9 on # GPIO3
+ end
+ device pnp 2e.a on # ACPI
+ end
+ device pnp 2e.b on # HW Monitor
+ io 0x60 = 0x290
+ irq 0x70 = 5
+ end
+ end
+ end
+ device pci 1.1 on end
+ device pci 1.2 on end
+ device pci 1.3 on
+ chip drivers/generic/generic # ???
+ device i2c 08 on end
+ end
+ chip drivers/i2c/i2cmux # pca9556 smbus mux
+ device i2c 18 on #0 pca9516 1
+ # I don't know what 30-33 are for,
+ # they seem to have something to do with the DIMM's
+ chip drivers/generic/generic # ???
+ device i2c 30 on end
+ end
+ chip drivers/generic/generic # ???
+ device i2c 31 on end
+ end
+ chip drivers/generic/generic # ???
+ device i2c 32 on end
+ end
+ chip drivers/generic/generic # ???
+ device i2c 33 on end
+ end
+ chip drivers/generic/generic #dimm H0-0
+ device i2c 50 on end
+ end
+ chip drivers/generic/generic #dimm H0-1
+ device i2c 51 on end
+ end
+ chip drivers/generic/generic #dimm H0-2
+ device i2c 52 on end
+ end
+ chip drivers/generic/generic #dimm H0-3
+ device i2c 53 on end
+ end
+ end
+ device i2c 18 on #1 pca9516 2
+ chip drivers/generic/generic # ???
+ device i2c 30 on end
+ end
+ chip drivers/generic/generic # ???
+ device i2c 31 on end
+ end
+ chip drivers/generic/generic # ???
+ device i2c 32 on end
+ end
+ chip drivers/generic/generic # ???
+ device i2c 33 on end
+ end
+ chip drivers/generic/generic #dimm H1-0
+ device i2c 50 on end
+ end
+ chip drivers/generic/generic #dimm H1-1
+ device i2c 51 on end
+ end
+ chip drivers/generic/generic #dimm H1-2
+ device i2c 52 on end
+ end
+ chip drivers/generic/generic #dimm H1-3
+ device i2c 53 on end
+ end
+ end
+ end
+ chip drivers/generic/generic # ???
+ device i2c 69 on end
+ end
+ end # acpi
+ device pci 1.4 off end
+ device pci 1.5 off end # AC97 Audio
+ device pci 1.6 off end # MC97 Modem
+ register "ide0_enable" = "1"
+ register "ide1_enable" = "1"
+ end
+ end # device pci 18.0
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+ end
+ end
+end
+
diff --git a/src/mainboard/hp/dl145_g1/get_bus_conf.c b/src/mainboard/hp/dl145_g1/get_bus_conf.c
new file mode 100644
index 0000000000..562ba935d8
--- /dev/null
+++ b/src/mainboard/hp/dl145_g1/get_bus_conf.c
@@ -0,0 +1,128 @@
+#include <console/console.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <string.h>
+#include <stdint.h>
+#if CONFIG_LOGICAL_CPUS==1
+#include <cpu/amd/multicore.h>
+#endif
+
+#include <cpu/amd/amdk8_sysconf.h>
+#include <stdlib.h>
+
+
+// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
+//busnum is default
+unsigned char bus_isa = 5 ;
+unsigned char bus_8131_0 = 1;
+unsigned char bus_8131_1 = 2;
+unsigned char bus_8131_2 = 3;
+unsigned char bus_8111_0 = 1;
+unsigned char bus_8111_1 = 4;
+unsigned apicid_8111 ;
+unsigned apicid_8131_1;
+unsigned apicid_8131_2;
+
+unsigned pci1234x[] =
+{ //Here you only need to set value in pci1234 for HT-IO that could be installed or not
+ //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
+ 0x0000ff0,
+// 0x0000ff0,
+// 0x0000ff0,
+// 0x0000ff0,
+// 0x0000ff0,
+// 0x0000ff0,
+// 0x0000ff0,
+// 0x0000ff0
+};
+unsigned hcdnx[] =
+{ //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most
+ 0x20202020,
+// 0x20202020,
+// 0x20202020,
+// 0x20202020,
+// 0x20202020,
+// 0x20202020,
+// 0x20202020,
+// 0x20202020,
+};
+unsigned sbdn3;
+
+
+
+static unsigned get_bus_conf_done = 0;
+
+void get_bus_conf(void)
+{
+
+ unsigned apicid_base;
+
+ device_t dev;
+ int i;
+
+ if(get_bus_conf_done==1) return; //do it only once
+
+ get_bus_conf_done = 1;
+
+ sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
+ for(i=0;i<sysconf.hc_possible_num; i++) {
+ sysconf.pci1234[i] = pci1234x[i];
+ sysconf.hcdn[i] = hcdnx[i];
+ }
+
+ get_sblk_pci1234();
+
+ sysconf.sbdn = (sysconf.hcdn[0] >> 8) & 0xff;
+ sbdn3 = sysconf.hcdn[0] & 0xff;
+
+ bus_8131_0 = (sysconf.pci1234[0] >> 16) & 0xff;
+ bus_8111_0 = bus_8131_0;
+
+ /* 8111 */
+ dev = dev_find_slot(bus_8111_0, PCI_DEVFN(sysconf.sbdn,0));
+ if (dev) {
+ bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
+#if CONFIG_HT_CHAIN_END_UNITID_BASE >= CONFIG_HT_CHAIN_UNITID_BASE
+ bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+ bus_isa++;
+// printk(BIOS_DEBUG, "bus_isa=%d\n",bus_isa);
+#endif
+ }
+ else {
+ printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:03.0, using defaults\n", bus_8111_0);
+ }
+
+ /* 8131-1 */
+ dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,0));
+ if (dev) {
+ bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
+ }
+ else {
+ printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:01.0, using defaults\n", bus_8131_0);
+ }
+
+ /* 8132-2 */
+ dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,0));
+ if (dev) {
+ bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
+#if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE
+ bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+ bus_isa++;
+// printk(BIOS_DEBUG, "bus_isa=%d\n",bus_isa);
+#endif
+ }
+ else {
+ printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:02.0, using defaults\n", bus_8131_0);
+ }
+
+
+/*I/O APICs: APIC ID Version State Address*/
+#if CONFIG_LOGICAL_CPUS==1
+ apicid_base = get_apicid_base(3);
+#else
+ apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
+#endif
+ apicid_8111 = apicid_base+0;
+ apicid_8131_1 = apicid_base+1;
+ apicid_8131_2 = apicid_base+2;
+}
diff --git a/src/mainboard/hp/dl145_g1/irq_tables.c b/src/mainboard/hp/dl145_g1/irq_tables.c
new file mode 100644
index 0000000000..b53a9923a7
--- /dev/null
+++ b/src/mainboard/hp/dl145_g1/irq_tables.c
@@ -0,0 +1,107 @@
+/* This file was generated by getpir.c, do not modify!
+ (but if you do, please run checkpir on it to verify)
+ Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up
+
+ Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
+*/
+#include <console/console.h>
+#include <device/pci.h>
+#include <string.h>
+#include <stdint.h>
+#include <arch/pirq_routing.h>
+
+#include <cpu/amd/amdk8_sysconf.h>
+
+static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0,
+ uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3,
+ uint8_t slot, uint8_t rfu)
+{
+ pirq_info->bus = bus;
+ pirq_info->devfn = devfn;
+ pirq_info->irq[0].link = link0;
+ pirq_info->irq[0].bitmap = bitmap0;
+ pirq_info->irq[1].link = link1;
+ pirq_info->irq[1].bitmap = bitmap1;
+ pirq_info->irq[2].link = link2;
+ pirq_info->irq[2].bitmap = bitmap2;
+ pirq_info->irq[3].link = link3;
+ pirq_info->irq[3].bitmap = bitmap3;
+ pirq_info->slot = slot;
+ pirq_info->rfu = rfu;
+}
+
+extern unsigned char bus_8131_0;
+extern unsigned char bus_8131_1;
+extern unsigned char bus_8131_2;
+extern unsigned char bus_8111_0;
+extern unsigned char bus_8111_1;
+
+extern unsigned sbdn3;
+
+
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+
+ struct irq_routing_table *pirq;
+ struct irq_info *pirq_info;
+ unsigned slot_num;
+ uint8_t *v;
+
+ uint8_t sum=0;
+ int i;
+
+ get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
+
+ /* Align the table to be 16 byte aligned. */
+ addr += 15;
+ addr &= ~15;
+
+ /* This table must be betweeen 0xf0000 & 0x100000 */
+ printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
+
+ pirq = (void *)(addr);
+ v = (uint8_t *)(addr);
+
+ pirq->signature = PIRQ_SIGNATURE;
+ pirq->version = PIRQ_VERSION;
+
+ pirq->rtr_bus = bus_8111_0;
+ pirq->rtr_devfn = ((sysconf.sbdn+1)<<3)|0;
+
+ pirq->exclusive_irqs = 0;
+
+ pirq->rtr_vendor = 0x1022;
+ pirq->rtr_device = 0x746b;
+
+ pirq->miniport_data = 0;
+
+ memset(pirq->rfu, 0, sizeof(pirq->rfu));
+
+ pirq_info = (void *) ( &pirq->checksum + 1);
+ slot_num = 0;
+//pci bridge
+ write_pirq_info(pirq_info, bus_8111_0, ((sysconf.sbdn+1)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
+ pirq_info++; slot_num++;
+//pcix bridge
+// write_pirq_info(pirq_info, bus_8131_0, (sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
+// pirq_info++; slot_num++;
+
+ pirq_info++; slot_num++;
+
+ pirq->size = 32 + 16 * slot_num;
+
+ for (i = 0; i < pirq->size; i++)
+ sum += v[i];
+
+ sum = pirq->checksum - sum;
+
+ if (sum != pirq->checksum) {
+ pirq->checksum = sum;
+ }
+
+ printk(BIOS_INFO, "done.\n");
+
+ return (unsigned long) pirq_info;
+
+}
diff --git a/src/mainboard/hp/dl145_g1/mainboard.c b/src/mainboard/hp/dl145_g1/mainboard.c
new file mode 100644
index 0000000000..922afe8fd7
--- /dev/null
+++ b/src/mainboard/hp/dl145_g1/mainboard.c
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2005 Tyan
+ * (Written by Yinghai Lu <yhlu@tyan.com> for Tyan)
+ * Copyright (C) 2007 Ward Vandewege <ward@gnu.org>
+ * Copyright (C) 2010 FOI Oskar Enoksson <oskeno@foi.se>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+#include "chip.h"
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("HP DL145G1 Mainboard")
+};
diff --git a/src/mainboard/hp/dl145_g1/mptable.c b/src/mainboard/hp/dl145_g1/mptable.c
new file mode 100644
index 0000000000..614ef48ba9
--- /dev/null
+++ b/src/mainboard/hp/dl145_g1/mptable.c
@@ -0,0 +1,132 @@
+#include <console/console.h>
+#include <arch/smp/mpspec.h>
+#include <device/pci.h>
+#include <string.h>
+#include <stdint.h>
+
+#include <cpu/amd/amdk8_sysconf.h>
+
+extern unsigned char bus_isa;
+extern unsigned char bus_8131_0;
+extern unsigned char bus_8131_1;
+extern unsigned char bus_8131_2;
+extern unsigned char bus_8111_0;
+extern unsigned char bus_8111_1;
+extern unsigned apicid_8111;
+extern unsigned apicid_8131_1;
+extern unsigned apicid_8131_2;
+
+extern unsigned sbdn3;
+
+
+
+static void *smp_write_config_table(void *v)
+{
+ static const char sig[4] = "PCMP";
+ static const char oem[8] = "COREBOOT";
+ static const char productid[12] = "DL145G1 ";
+ struct mp_config_table *mc;
+
+ unsigned char bus_num;
+
+ int i;
+
+ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+ memset(mc, 0, sizeof(*mc));
+
+ memcpy(mc->mpc_signature, sig, sizeof(sig));
+ mc->mpc_length = sizeof(*mc); /* initially just the header */
+ mc->mpc_spec = 0x04;
+ mc->mpc_checksum = 0; /* not yet computed */
+ memcpy(mc->mpc_oem, oem, sizeof(oem));
+ memcpy(mc->mpc_productid, productid, sizeof(productid));
+ mc->mpc_oemptr = 0;
+ mc->mpc_oemsize = 0;
+ mc->mpc_entry_count = 0; /* No entries yet... */
+ mc->mpc_lapic = LAPIC_ADDR;
+ mc->mpe_length = 0;
+ mc->mpe_checksum = 0;
+ mc->reserved = 0;
+
+ smp_write_processors(mc);
+
+ get_bus_conf();
+
+
+/*Bus: Bus ID Type*/
+ /* define bus and isa numbers */
+ for(bus_num = 0; bus_num < bus_isa; bus_num++) {
+ smp_write_bus(mc, bus_num, "PCI ");
+ }
+ smp_write_bus(mc, bus_isa, "ISA ");
+
+
+/*I/O APICs: APIC ID Version State Address*/
+ smp_write_ioapic(mc, apicid_8111, 0x20, 0xfec00000);
+ {
+ device_t dev;
+ struct resource *res;
+ dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,1));
+ if (dev) {
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ if (res) {
+ smp_write_ioapic(mc, apicid_8131_1, 0x20, res->base);
+ }
+ }
+ dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,1));
+ if (dev) {
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ if (res) {
+ smp_write_ioapic(mc, apicid_8131_2, 0x20, res->base);
+ }
+ }
+
+ }
+
+ mptable_add_isa_interrupts(mc, bus_isa, apicid_8111, 0);
+
+ //
+ // The commented-out lines are auto-detected on my servers.
+ //
+/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
+ // Integrated SMBus 2.0
+ //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ( 0x4 <<2)|3, apicid_8111 , 0x15);
+ // Integrated AMD AC97 Audio
+ //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ( 0x4 <<2)|1, apicid_8111 , 0x11);
+ //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ( 0x4 <<2)|2, apicid_8111 , 0x12);
+ // Integrated AMD USB
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, ( 0x4 <<2)|0, apicid_8111 , 0x10);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, ( 0x0 <<2)|3, apicid_8111 , 0x13);
+ // On board ATI Rage XL
+ //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, ( 0x5 <<2)|0, apicid_8111 , 0x14);
+ // On board Broadcom nics
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, ( 0x3 <<2)|0, apicid_8131_2, 0x03);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, ( 0x3 <<2)|1, apicid_8131_2, 0x00);
+ // On board LSI SCSI
+ //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, ( 0x2 <<2)|0, apicid_8131_2, 0x02);
+
+ // PCIX-133 Slot
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, ( 0x1 <<2)|0, apicid_8131_1, 0x01);
+ //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, ( 0x1 <<2)|1, apicid_8131_1, 0x02);
+ //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, ( 0x1 <<2)|2, apicid_8131_1, 0x03);
+ //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, ( 0x1 <<2)|3, apicid_8131_1, 0x04);
+
+/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
+ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
+ smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
+ /* There is no extension information... */
+
+ /* Compute the checksums */
+ mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
+ mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
+ printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
+ mc, smp_next_mpe_entry(mc));
+ return smp_next_mpe_entry(mc);
+}
+
+unsigned long write_smp_table(unsigned long addr)
+{
+ void *v;
+ v = smp_write_floating_table(addr);
+ return (unsigned long)smp_write_config_table(v);
+}
diff --git a/src/mainboard/hp/dl145_g1/resourcemap.c b/src/mainboard/hp/dl145_g1/resourcemap.c
new file mode 100644
index 0000000000..9a9fb10186
--- /dev/null
+++ b/src/mainboard/hp/dl145_g1/resourcemap.c
@@ -0,0 +1,266 @@
+/*
+ * DL145G1 needs a different resource map
+ * This file may need more tweaking, it is copied from the Tyan S2881 mainboard
+ */
+
+static void setup_dl145g1_resource_map(void)
+{
+ static const unsigned int register_values[] = {
+ /* Careful set limit registers before base registers which contain the enables */
+ /* DRAM Limit i Registers
+ * F1:0x44 i = 0
+ * F1:0x4C i = 1
+ * F1:0x54 i = 2
+ * F1:0x5C i = 3
+ * F1:0x64 i = 4
+ * F1:0x6C i = 5
+ * F1:0x74 i = 6
+ * F1:0x7C i = 7
+ * [ 2: 0] Destination Node ID
+ * 000 = Node 0
+ * 001 = Node 1
+ * 010 = Node 2
+ * 011 = Node 3
+ * 100 = Node 4
+ * 101 = Node 5
+ * 110 = Node 6
+ * 111 = Node 7
+ * [ 7: 3] Reserved
+ * [10: 8] Interleave select
+ * specifies the values of A[14:12] to use with interleave enable.
+ * [15:11] Reserved
+ * [31:16] DRAM Limit Address i Bits 39-24
+ * This field defines the upper address bits of a 40 bit address
+ * that define the end of the DRAM region.
+ */
+ PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
+ PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
+ PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
+ PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
+ PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
+ PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
+ PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
+ /* DRAM Base i Registers
+ * F1:0x40 i = 0
+ * F1:0x48 i = 1
+ * F1:0x50 i = 2
+ * F1:0x58 i = 3
+ * F1:0x60 i = 4
+ * F1:0x68 i = 5
+ * F1:0x70 i = 6
+ * F1:0x78 i = 7
+ * [ 0: 0] Read Enable
+ * 0 = Reads Disabled
+ * 1 = Reads Enabled
+ * [ 1: 1] Write Enable
+ * 0 = Writes Disabled
+ * 1 = Writes Enabled
+ * [ 7: 2] Reserved
+ * [10: 8] Interleave Enable
+ * 000 = No interleave
+ * 001 = Interleave on A[12] (2 nodes)
+ * 010 = reserved
+ * 011 = Interleave on A[12] and A[14] (4 nodes)
+ * 100 = reserved
+ * 101 = reserved
+ * 110 = reserved
+ * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
+ * [15:11] Reserved
+ * [13:16] DRAM Base Address i Bits 39-24
+ * This field defines the upper address bits of a 40-bit address
+ * that define the start of the DRAM region.
+ */
+ PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
+
+ /* Memory-Mapped I/O Limit i Registers
+ * F1:0x84 i = 0
+ * F1:0x8C i = 1
+ * F1:0x94 i = 2
+ * F1:0x9C i = 3
+ * F1:0xA4 i = 4
+ * F1:0xAC i = 5
+ * F1:0xB4 i = 6
+ * F1:0xBC i = 7
+ * [ 2: 0] Destination Node ID
+ * 000 = Node 0
+ * 001 = Node 1
+ * 010 = Node 2
+ * 011 = Node 3
+ * 100 = Node 4
+ * 101 = Node 5
+ * 110 = Node 6
+ * 111 = Node 7
+ * [ 3: 3] Reserved
+ * [ 5: 4] Destination Link ID
+ * 00 = Link 0
+ * 01 = Link 1
+ * 10 = Link 2
+ * 11 = Reserved
+ * [ 6: 6] Reserved
+ * [ 7: 7] Non-Posted
+ * 0 = CPU writes may be posted
+ * 1 = CPU writes must be non-posted
+ * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
+ * This field defines the upp adddress bits of a 40-bit address that
+ * defines the end of a memory-mapped I/O region n
+ */
+ PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,
+ //PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000b20,
+ PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff20,
+
+ /* Memory-Mapped I/O Base i Registers
+ * F1:0x80 i = 0
+ * F1:0x88 i = 1
+ * F1:0x90 i = 2
+ * F1:0x98 i = 3
+ * F1:0xA0 i = 4
+ * F1:0xA8 i = 5
+ * F1:0xB0 i = 6
+ * F1:0xB8 i = 7
+ * [ 0: 0] Read Enable
+ * 0 = Reads disabled
+ * 1 = Reads Enabled
+ * [ 1: 1] Write Enable
+ * 0 = Writes disabled
+ * 1 = Writes Enabled
+ * [ 2: 2] Cpu Disable
+ * 0 = Cpu can use this I/O range
+ * 1 = Cpu requests do not use this I/O range
+ * [ 3: 3] Lock
+ * 0 = base/limit registers i are read/write
+ * 1 = base/limit registers i are read-only
+ * [ 7: 4] Reserved
+ * [31: 8] Memory-Mapped I/O Base Address i (39-16)
+ * This field defines the upper address bits of a 40bit address
+ * that defines the start of memory-mapped I/O region i
+ */
+ PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,
+ //PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000a03,
+ PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003,
+
+ /* PCI I/O Limit i Registers
+ * F1:0xC4 i = 0
+ * F1:0xCC i = 1
+ * F1:0xD4 i = 2
+ * F1:0xDC i = 3
+ * [ 2: 0] Destination Node ID
+ * 000 = Node 0
+ * 001 = Node 1
+ * 010 = Node 2
+ * 011 = Node 3
+ * 100 = Node 4
+ * 101 = Node 5
+ * 110 = Node 6
+ * 111 = Node 7
+ * [ 3: 3] Reserved
+ * [ 5: 4] Destination Link ID
+ * 00 = Link 0
+ * 01 = Link 1
+ * 10 = Link 2
+ * 11 = reserved
+ * [11: 6] Reserved
+ * [24:12] PCI I/O Limit Address i
+ * This field defines the end of PCI I/O region n
+ * [31:25] Reserved
+ */
+ PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff020,
+ PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
+
+ /* PCI I/O Base i Registers
+ * F1:0xC0 i = 0
+ * F1:0xC8 i = 1
+ * F1:0xD0 i = 2
+ * F1:0xD8 i = 3
+ * [ 0: 0] Read Enable
+ * 0 = Reads Disabled
+ * 1 = Reads Enabled
+ * [ 1: 1] Write Enable
+ * 0 = Writes Disabled
+ * 1 = Writes Enabled
+ * [ 3: 2] Reserved
+ * [ 4: 4] VGA Enable
+ * 0 = VGA matches Disabled
+ * 1 = matches all address < 64K and where A[9:0] is in the
+ * range 3B0-3BB or 3C0-3DF independen of the base & limit registers
+ * [ 5: 5] ISA Enable
+ * 0 = ISA matches Disabled
+ * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
+ * from matching agains this base/limit pair
+ * [11: 6] Reserved
+ * [24:12] PCI I/O Base i
+ * This field defines the start of PCI I/O region n
+ * [31:25] Reserved
+ */
+ PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003,
+ PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
+
+ /* Config Base and Limit i Registers
+ * F1:0xE0 i = 0
+ * F1:0xE4 i = 1
+ * F1:0xE8 i = 2
+ * F1:0xEC i = 3
+ * [ 0: 0] Read Enable
+ * 0 = Reads Disabled
+ * 1 = Reads Enabled
+ * [ 1: 1] Write Enable
+ * 0 = Writes Disabled
+ * 1 = Writes Enabled
+ * [ 2: 2] Device Number Compare Enable
+ * 0 = The ranges are based on bus number
+ * 1 = The ranges are ranges of devices on bus 0
+ * [ 3: 3] Reserved
+ * [ 6: 4] Destination Node
+ * 000 = Node 0
+ * 001 = Node 1
+ * 010 = Node 2
+ * 011 = Node 3
+ * 100 = Node 4
+ * 101 = Node 5
+ * 110 = Node 6
+ * 111 = Node 7
+ * [ 7: 7] Reserved
+ * [ 9: 8] Destination Link
+ * 00 = Link 0
+ * 01 = Link 1
+ * 10 = Link 2
+ * 11 - Reserved
+ * [15:10] Reserved
+ * [23:16] Bus Number Base i
+ * This field defines the lowest bus number in configuration region i
+ * [31:24] Bus Number Limit i
+ * This field defines the highest bus number in configuration regin i
+ */
+ PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000203,
+ PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
+ };
+ int max;
+ max = ARRAY_SIZE(register_values);
+ setup_resource_map(register_values, max);
+}
+
diff --git a/src/mainboard/hp/dl145_g1/romstage.c b/src/mainboard/hp/dl145_g1/romstage.c
new file mode 100644
index 0000000000..f9f0def783
--- /dev/null
+++ b/src/mainboard/hp/dl145_g1/romstage.c
@@ -0,0 +1,207 @@
+#define QRANK_DIMM_SUPPORT 1
+
+#if CONFIG_LOGICAL_CPUS==1
+#define SET_NB_CFG_54 1
+#endif
+
+#include <stdint.h>
+#include <string.h>
+#include <device/pci_def.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/romcc_io.h>
+#include <cpu/x86/lapic.h>
+#include <pc80/mc146818rtc.h>
+#include <console/console.h>
+#include "lib/ramtest.c"
+
+#include <cpu/amd/model_fxx_rev.h>
+
+#include "northbridge/amd/amdk8/incoherent_ht.c"
+#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
+#include "northbridge/amd/amdk8/raminit.h"
+#include "cpu/amd/model_fxx/apic_timer.c"
+#include "lib/delay.c"
+
+#include "cpu/x86/lapic/boot_cpu.c"
+#include "northbridge/amd/amdk8/reset_test.c"
+#include "northbridge/amd/amdk8/debug.c"
+#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
+
+#include "cpu/x86/mtrr/earlymtrr.c"
+#include "cpu/x86/bist.h"
+
+#include "northbridge/amd/amdk8/setup_resource_map.c"
+
+#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
+
+#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
+
+static void memreset_setup(void)
+{
+ if (is_cpu_pre_c0()) {
+ /* Set the memreset low */
+ outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);
+ /* Ensure the BIOS has control of the memory lines */
+ outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
+ } else {
+ /* Ensure the CPU has controll of the memory lines */
+ outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17);
+ }
+}
+
+static void memreset(int controllers, const struct mem_controller *ctrl)
+{
+ if (is_cpu_pre_c0()) {
+ udelay(800);
+ /* Set memreset_high */
+ outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);
+ udelay(90);
+ }
+}
+
+#define SMBUS_HUB 0x18
+
+static inline void activate_spd_rom(const struct mem_controller *ctrl)
+{
+ int ret,i;
+ unsigned device=(ctrl->channel0[0])>>8;
+ /* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/
+ i=2;
+ do {
+ ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
+ } while ((ret!=0) && (i-->0));
+
+ smbus_write_byte(SMBUS_HUB, 0x03, 0);
+}
+
+static inline void change_i2c_mux(unsigned device)
+{
+ int ret, i;
+ print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n");
+ i=2;
+ do {
+ ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
+ print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\n");
+ } while ((ret!=0) && (i-->0));
+ ret = smbus_write_byte(SMBUS_HUB, 0x03, 0);
+ print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\n");
+}
+
+static inline int spd_read_byte(unsigned device, unsigned address)
+{
+ return smbus_read_byte(device, address);
+}
+
+#include "northbridge/amd/amdk8/raminit.c"
+#include "resourcemap.c"
+#include "northbridge/amd/amdk8/resourcemap.c"
+#include "northbridge/amd/amdk8/coherent_ht.c"
+#include "lib/generic_sdram.c"
+
+#include "cpu/amd/dualcore/dualcore.c"
+
+#define RC0 ((1<<1)<<8) // Not sure about these values
+#define RC1 ((1<<2)<<8) // Not sure about these values
+
+#define DIMM0 0x50
+#define DIMM1 0x51
+#define DIMM2 0x52
+#define DIMM3 0x53
+
+#include "cpu/amd/car/post_cache_as_ram.c"
+
+#include "cpu/amd/model_fxx/init_cpus.c"
+
+#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
+#include "northbridge/amd/amdk8/early_ht.c"
+
+
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+ static const uint16_t spd_addr [] = {
+ //first node
+ RC0|DIMM0, RC0|DIMM2, 0, 0,
+ RC0|DIMM1, RC0|DIMM3, 0, 0,
+#if CONFIG_MAX_PHYSICAL_CPUS > 1
+ //second node
+ RC1|DIMM0, RC1|DIMM2, 0, 0,
+ RC1|DIMM1, RC1|DIMM3, 0, 0,
+#endif
+ };
+
+ int needs_reset;
+ unsigned bsp_apicid = 0;
+
+ struct mem_controller ctrl[8];
+ unsigned nodes;
+
+ if (!cpu_init_detectedx && boot_cpu()) {
+ /* Nothing special needs to be done to find bus 0 */
+ /* Allow the HT devices to be found */
+
+ enumerate_ht_chain();
+
+ /* Setup the amd8111 */
+ amd8111_enable_rom();
+ }
+
+ if (bist == 0) {
+ bsp_apicid = init_cpus(cpu_init_detectedx);
+ }
+
+// post_code(0x32);
+
+ w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ uart_init();
+ console_init();
+
+ /* Halt if there was a built in self test failure */
+ report_bist_failure(bist);
+
+ setup_dl145g1_resource_map();
+ //setup_default_resource_map();
+
+ needs_reset = setup_coherent_ht_domain();
+
+ wait_all_core0_started();
+#if CONFIG_LOGICAL_CPUS==1
+ // It is said that we should start core1 after all core0 launched
+ start_other_cores();
+ wait_all_other_cores_started(bsp_apicid);
+#endif
+
+ needs_reset |= ht_setup_chains_x();
+
+ if (needs_reset) {
+ print_info("ht reset -\n");
+ soft_reset();
+ }
+
+ enable_smbus();
+
+ int i;
+ for(i=0;i<2;i++) {
+ activate_spd_rom(&ctrl[i]);
+ }
+ for(i=2;i<8;i<<=1) {
+ change_i2c_mux(i);
+ }
+
+ //dump_spd_registers(&ctrl[0]);
+ //dump_spd_registers(&ctrl[1]);
+ //dump_smbus_registers();
+
+ allow_all_aps_stop(bsp_apicid);
+
+ nodes = get_nodes();
+ //It's the time to set ctrl now;
+ fill_mem_ctrl(nodes, ctrl, spd_addr);
+
+ memreset_setup();
+ sdram_initialize(nodes, ctrl);
+
+ //dump_pci_devices();
+
+ post_cache_as_ram();
+}