summaryrefslogtreecommitdiff
path: root/src/mainboard
diff options
context:
space:
mode:
authorChris Wang <chris.wang@amd.corp-partner.google.com>2018-11-22 00:03:29 +0800
committerMartin Roth <martinroth@google.com>2018-11-23 21:52:28 +0000
commit386b084ee187e7705d16c7f67f28b62d02eb9ca9 (patch)
tree4db2dc4213eff5cb097ba07aeb34e579e968fda2 /src/mainboard
parentcaf6d0bc5239c4e9fd72b98cfe8b3d47d19a3616 (diff)
downloadcoreboot-386b084ee187e7705d16c7f67f28b62d02eb9ca9.tar.xz
mb/google/kahlee: Enable 2T mode for liara in DVT phase
Change the board id detection to support rev5, since the 2T mode still needed in DVT build. BUG=b:116082728 TEST=verify by ODM. Change-Id: Ibb4cc1fd2bb54984cb7a8856ed7b9f49b78eddce Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/29779 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/kahlee/OemCustomize.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/kahlee/OemCustomize.c b/src/mainboard/google/kahlee/OemCustomize.c
index 12e50724ec..fc8ff32901 100644
--- a/src/mainboard/google/kahlee/OemCustomize.c
+++ b/src/mainboard/google/kahlee/OemCustomize.c
@@ -58,7 +58,7 @@ static const PSO_ENTRY DDR4LiaraMemoryConfiguration[] = {
void OemPostParams(AMD_POST_PARAMS *PostParams)
{
- if ((IS_ENABLED(CONFIG_BOARD_GOOGLE_LIARA)) && (board_id() <= 4))
+ if ((IS_ENABLED(CONFIG_BOARD_GOOGLE_LIARA)) && (board_id() <= 5))
PostParams->MemConfig.PlatformMemoryConfiguration =
(PSO_ENTRY *)DDR4LiaraMemoryConfiguration;
else