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authorEdward O'Callaghan <eocallaghan@alterapraxis.com>2014-10-29 06:15:57 +1100
committerEdward O'Callaghan <eocallaghan@alterapraxis.com>2014-10-28 23:02:44 +0100
commit38b98546a7ae1b795d8f2c1b9647af77e508edd4 (patch)
tree89d0f569c289328caeb1eb4910bca8f595943ade /src/mainboard
parent9b63c9bde2fc3b3a2d42e68618e043cf282bc566 (diff)
downloadcoreboot-38b98546a7ae1b795d8f2c1b9647af77e508edd4.tar.xz
mainboard/google/butterfly: Fix usage of GNU field designator ext
Following the reasoning in, 8089f17 mainboard/lenovo/x230 Fix usage of GNU field designator extension In C99 we defined a syntax for this. GCC's old syntax was deprecated. Change-Id: I167d2c9ad3f690de41fee51dd7800ce76b328e41 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7231 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/butterfly/romstage.c48
1 files changed, 24 insertions, 24 deletions
diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c
index 908b6d869e..6b7613a85b 100644
--- a/src/mainboard/google/butterfly/romstage.c
+++ b/src/mainboard/google/butterfly/romstage.c
@@ -119,33 +119,33 @@ void main(unsigned long bist)
int cbmem_was_initted;
struct pei_data pei_data = {
- pei_version: PEI_VERSION,
- mchbar: DEFAULT_MCHBAR,
- dmibar: DEFAULT_DMIBAR,
- epbar: DEFAULT_EPBAR,
- pciexbar: CONFIG_MMCONF_BASE_ADDRESS,
- smbusbar: SMBUS_IO_BASE,
- wdbbar: 0x4000000,
- wdbsize: 0x1000,
- hpet_address: CONFIG_HPET_ADDRESS,
- rcba: DEFAULT_RCBABASE,
- pmbase: DEFAULT_PMBASE,
- gpiobase: DEFAULT_GPIOBASE,
- thermalbase: 0xfed08000,
- system_type: 0, // 0 Mobile, 1 Desktop/Server
- tseg_size: CONFIG_SMM_TSEG_SIZE,
- spd_addresses: { 0xA0, 0x00,0xA4,0x00 },
- ts_addresses: { 0x00, 0x00, 0x00, 0x00 },
- ec_present: 1,
- ddr3lv_support: 0,
+ .pei_version = PEI_VERSION,
+ .mchbar = DEFAULT_MCHBAR,
+ .dmibar = DEFAULT_DMIBAR,
+ .epbar = DEFAULT_EPBAR,
+ .pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
+ .smbusbar = SMBUS_IO_BASE,
+ .wdbbar = 0x4000000,
+ .wdbsize = 0x1000,
+ .hpet_address = CONFIG_HPET_ADDRESS,
+ .rcba = DEFAULT_RCBABASE,
+ .pmbase = DEFAULT_PMBASE,
+ .gpiobase = DEFAULT_GPIOBASE,
+ .thermalbase = 0xfed08000,
+ .system_type = 0, // 0 Mobile, 1 Desktop/Server
+ .tseg_size = CONFIG_SMM_TSEG_SIZE,
+ .spd_addresses = { 0xA0, 0x00,0xA4,0x00 },
+ .ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
+ .ec_present = 1,
+ .ddr3lv_support = 0,
// 0 = leave channel enabled
// 1 = disable dimm 0 on channel
// 2 = disable dimm 1 on channel
// 3 = disable dimm 0+1 on channel
- dimm_channel0_disabled: 2,
- dimm_channel1_disabled: 2,
- max_ddr3_freq: 1600,
- usb_port_config: {
+ .dimm_channel0_disabled = 2,
+ .dimm_channel1_disabled = 2,
+ .max_ddr3_freq = 1600,
+ .usb_port_config = {
/* enabled usb oc pin length */
{ 1, 0, 0x0040 }, /* P0: Right USB 3.0 #1 (no OC) */
{ 1, 0, 0x0040 }, /* P1: Right USB 3.0 #2 (no OC) */
@@ -162,7 +162,7 @@ void main(unsigned long bist)
{ 0, 4, 0x0000 }, /* P12: Empty */
{ 0, 4, 0x0000 }, /* P13: Empty */
},
- ddr_refresh_rate_config: 2, /* Force double refresh rate */
+ .ddr_refresh_rate_config = 2, /* Force double refresh rate */
};
timestamp_init(get_initial_timestamp());