summaryrefslogtreecommitdiff
path: root/src/mainboard
diff options
context:
space:
mode:
authorV Sowmya <v.sowmya@intel.com>2020-06-30 20:22:26 +0530
committerKarthik Ramasubramanian <kramasub@google.com>2020-07-23 04:54:14 +0000
commit391562761527fc6de0144a97cca3d19b105a45cb (patch)
treeff174c5e009e6e894b9f5a0352f7e3ca0c3f7e9f /src/mainboard
parente8156ad9818111a58e0d54e27b74e083c1d4f856 (diff)
downloadcoreboot-391562761527fc6de0144a97cca3d19b105a45cb.tar.xz
mb/google/dedede: Skip the CPU replacement check for dedede
This patches enables the SkipCpuReplacementCheck config for the dedede baseboard to avoid the forced MRC training for all its variants with the soldered down SOC. BUG=b:160201335 TEST=Build and verify CSE Lite SKU on Waddledoo. Cq-Depend: chrome-internal:3142530 Change-Id: I611e66f74a3b9b090ab5e0d836231643d3f919dc Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42930 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/dedede/variants/baseboard/devicetree.cb3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
index e126129f11..7502489c06 100644
--- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
@@ -163,6 +163,9 @@ chip soc/intel/jasperlake
# register "common_soc_config.<variable_name>" = "value"
register "common_soc_config.chipset_lockdown" = CHIPSET_LOCKDOWN_COREBOOT
+ # Skip the CPU repalcement check
+ register "SkipCpuReplacementCheck" = "1"
+
device domain 0 on
device pci 00.0 on end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device