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authorSumeet R Pawnikar <sumeet.r.pawnikar@intel.com>2020-09-08 11:30:46 +0530
committerPatrick Georgi <pgeorgi@google.com>2020-09-14 07:04:07 +0000
commit426e07aaf20ae917dd65997bf46667d56881444a (patch)
tree6505ebb00065f7d64593a88e2f74f2ed8cefbe38 /src/mainboard
parent033038fd489cb0e37303e765bfb077354714012e (diff)
downloadcoreboot-426e07aaf20ae917dd65997bf46667d56881444a.tar.xz
mb/google/dedede/variants/drawcia: Increase PL2 value from 15W to 20W
Jasper Lake SoC supports PL2 (Power Limit2) as 20W. Increase PL2 value from 15W to 20W. BRANCH=None BUG=b:166656373 TEST=Built and tested on drawlat system Change-Id: I82d6792907bb1c88cc9dd57d1eaeda8421c12fb2 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45162 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/dedede/variants/drawcia/overridetree.cb4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb
index 395dee3f69..fa10152a4e 100644
--- a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb
@@ -59,7 +59,7 @@ chip soc/intel/jasperlake
register "power_limits_config" = "{
.tdp_pl1_override = 6,
- .tdp_pl2_override = 15,
+ .tdp_pl2_override = 20,
}"
register "tcc_offset" = "20" # TCC of 85C
@@ -93,7 +93,7 @@ chip soc/intel/jasperlake
.granularity = 200,}"
register "controls.power_limits.pl2" = "{
.min_power = 6000,
- .max_power = 15000,
+ .max_power = 20000,
.time_window_min = 1 * MSECS_PER_SEC,
.time_window_max = 1 * MSECS_PER_SEC,
.granularity = 1000,}"