diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2019-10-31 08:22:34 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-01 11:57:44 +0000 |
| commit | 57248c2b8c680a8daa2cf2cb1b5938b8c52d5cdb (patch) | |
| tree | 2e0dae1e715c7d1160b599dfe51e14f8a9fc8caa /src/mainboard | |
| parent | 7011e546e1914f4de59b241e06bf3aeafd42efa3 (diff) | |
| download | coreboot-57248c2b8c680a8daa2cf2cb1b5938b8c52d5cdb.tar.xz | |
mb/apple/macbook21: Use DEBUG_RAM_SETUP
Also, the loglevel is never set to value of > 8.
Change-Id: Ief29e07be6ac075956bf0f9aee85b14eb89af44c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Evgeny Zinoviev <me@ch1p.io>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/apple/macbook21/romstage.c | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c index ee5ba80366..34cd378839 100644 --- a/src/mainboard/apple/macbook21/romstage.c +++ b/src/mainboard/apple/macbook21/romstage.c @@ -226,9 +226,8 @@ void mainboard_romstage_entry(void) /* Enable SPD ROMs and DDR-II DRAM */ enable_smbus(); -#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 - dump_spd_registers(); -#endif + if (CONFIG(DEBUG_RAM_SETUP)) + dump_spd_registers(); sdram_initialize(s3resume ? 2 : 0, spd_addrmap); |