diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2018-06-12 22:58:19 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-06-21 15:50:16 +0000 |
| commit | 58a89537931cd243c6ddbb9ff435bc5862fc64b0 (patch) | |
| tree | 513a5a682063919f1f6c99d638ba75e6fbc86c3a /src/mainboard | |
| parent | 4dfb5f1055b03d27a509272e1a68de45c3fa2266 (diff) | |
| download | coreboot-58a89537931cd243c6ddbb9ff435bc5862fc64b0.tar.xz | |
Revert "sb/intel/{bd82x6,ibexpeak}: Move RCBA macros to a common location"
In the end it does not look like RCBA register offsets are fully
compatible over southbridges.
This reverts commit d2d2aef6a3222af909183fb96dc7bc908fac3cd4.
Is squashed with revert of "sb/intel/common: Fix conflicting OIC
register definition" 8aaa00401b68e5c5b6c07b0984e3e7c3027e3c2f.
Change-Id: Icbf4db8590e60573c8c11385835e0231cf8d63e6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27038
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/mainboard')
34 files changed, 14 insertions, 46 deletions
diff --git a/src/mainboard/apple/macbookair4_2/early_southbridge.c b/src/mainboard/apple/macbookair4_2/early_southbridge.c index 25ddb9852b..b9cfa2023a 100644 --- a/src/mainboard/apple/macbookair4_2/early_southbridge.c +++ b/src/mainboard/apple/macbookair4_2/early_southbridge.c @@ -25,7 +25,6 @@ #include "northbridge/intel/sandybridge/sandybridge.h" #include "northbridge/intel/sandybridge/raminit_native.h" #include "southbridge/intel/bd82x6x/pch.h" -#include <southbridge/intel/common/rcba.h> #include <southbridge/intel/common/gpio.h> #include <arch/cpu.h> #include <cpu/x86/msr.h> diff --git a/src/mainboard/apple/macbookair4_2/mainboard.c b/src/mainboard/apple/macbookair4_2/mainboard.c index cd0ab81b36..3606e26e03 100644 --- a/src/mainboard/apple/macbookair4_2/mainboard.c +++ b/src/mainboard/apple/macbookair4_2/mainboard.c @@ -13,7 +13,6 @@ #include <device/device.h> #include <drivers/intel/gma/int15.h> -#include <southbridge/intel/common/rcba.h> #include <southbridge/intel/bd82x6x/pch.h> #include <ec/acpi/ec.h> #include <console/console.h> diff --git a/src/mainboard/compulab/intense_pc/romstage.c b/src/mainboard/compulab/intense_pc/romstage.c index f690efa197..58a78d0f90 100644 --- a/src/mainboard/compulab/intense_pc/romstage.c +++ b/src/mainboard/compulab/intense_pc/romstage.c @@ -18,7 +18,6 @@ #include <arch/io.h> #include "northbridge/intel/sandybridge/raminit_native.h" #include <superio/smsc/sio1007/chip.h> -#include <southbridge/intel/common/rcba.h> #define SIO_PORT 0x164e diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c b/src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c index 7bc353c035..90131ffe08 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c +++ b/src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c @@ -27,7 +27,6 @@ #include <arch/io.h> #include <arch/interrupt.h> #include <boot/coreboot_tables.h> -#include <southbridge/intel/common/rcba.h> #include <southbridge/intel/bd82x6x/pch.h> #include <smbios.h> #include <device/pci.h> diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c index 92bef2882f..5a2c935d5a 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c +++ b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c @@ -28,7 +28,6 @@ #include <superio/ite/common/ite.h> #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit_native.h> -#include <southbridge/intel/common/rcba.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> #include <arch/cpu.h> diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/mainboard.c b/src/mainboard/gigabyte/ga-b75m-d3v/mainboard.c index 7bc353c035..90131ffe08 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3v/mainboard.c +++ b/src/mainboard/gigabyte/ga-b75m-d3v/mainboard.c @@ -27,7 +27,6 @@ #include <arch/io.h> #include <arch/interrupt.h> #include <boot/coreboot_tables.h> -#include <southbridge/intel/common/rcba.h> #include <southbridge/intel/bd82x6x/pch.h> #include <smbios.h> #include <device/pci.h> diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c index 283ad46dca..a389e68f0d 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c +++ b/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c @@ -28,7 +28,6 @@ #include <superio/ite/common/ite.h> #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit_native.h> -#include <southbridge/intel/common/rcba.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> #include <arch/cpu.h> diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c index ebcba8409c..3ef4659a5a 100644 --- a/src/mainboard/google/butterfly/romstage.c +++ b/src/mainboard/google/butterfly/romstage.c @@ -29,7 +29,6 @@ #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit.h> #include <northbridge/intel/sandybridge/raminit_native.h> -#include <southbridge/intel/common/rcba.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> #include <arch/cpu.h> @@ -96,9 +95,9 @@ void mainboard_rcba_config(void) DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); /* Enable IOAPIC (generic) */ - RCBA16(EOIC) = 0x0100; + RCBA16(OIC) = 0x0100; /* PCH BWG says to read back the IOAPIC enable register */ - (void) RCBA16(EOIC); + (void) RCBA16(OIC); /* Disable unused devices (board specific) */ reg32 = RCBA32(FD); diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c index cc2ef22ab6..d9f00f4bc3 100644 --- a/src/mainboard/google/link/romstage.c +++ b/src/mainboard/google/link/romstage.c @@ -30,7 +30,6 @@ #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit.h> #include <northbridge/intel/sandybridge/raminit_native.h> -#include <southbridge/intel/common/rcba.h> #include <southbridge/intel/common/gpio.h> #include "ec/google/chromeec/ec.h" #include <arch/cpu.h> @@ -104,9 +103,9 @@ void mainboard_rcba_config(void) DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); /* Enable IOAPIC (generic) */ - RCBA16(EOIC) = 0x0100; + RCBA16(OIC) = 0x0100; /* PCH BWG says to read back the IOAPIC enable register */ - (void) RCBA16(EOIC); + (void) RCBA16(OIC); } static uint8_t *locate_spd(void) diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c index 30fa7c22b8..6163c35e02 100644 --- a/src/mainboard/google/parrot/romstage.c +++ b/src/mainboard/google/parrot/romstage.c @@ -29,7 +29,6 @@ #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit.h> #include <northbridge/intel/sandybridge/raminit_native.h> -#include <southbridge/intel/common/rcba.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> #include <arch/cpu.h> @@ -95,9 +94,9 @@ void mainboard_rcba_config(void) DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); /* Enable IOAPIC (generic) */ - RCBA16(EOIC) = 0x0100; + RCBA16(OIC) = 0x0100; /* PCH BWG says to read back the IOAPIC enable register */ - (void) RCBA16(EOIC); + (void) RCBA16(OIC); /* Disable unused devices (board specific) */ reg32 = RCBA32(FD); diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c index 9ad03f7366..36ebcf7d36 100644 --- a/src/mainboard/google/stout/romstage.c +++ b/src/mainboard/google/stout/romstage.c @@ -29,7 +29,6 @@ #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit.h> #include <northbridge/intel/sandybridge/raminit_native.h> -#include <southbridge/intel/common/rcba.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> #include <arch/cpu.h> @@ -101,9 +100,9 @@ void mainboard_rcba_config(void) DIR_ROUTE(D20IR, PIRQD, PIRQE, PIRQF, PIRQG); /* Enable IOAPIC (generic) */ - RCBA16(EOIC) = 0x0100; + RCBA16(OIC) = 0x0100; /* PCH BWG says to read back the IOAPIC enable register */ - (void) RCBA16(EOIC); + (void) RCBA16(OIC); /* Disable unused devices (board specific) */ reg32 = RCBA32(FD); diff --git a/src/mainboard/hp/folio_9470m/romstage.c b/src/mainboard/hp/folio_9470m/romstage.c index 3364de10fe..1994c4fa37 100644 --- a/src/mainboard/hp/folio_9470m/romstage.c +++ b/src/mainboard/hp/folio_9470m/romstage.c @@ -18,7 +18,6 @@ #include <arch/io.h> #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit_native.h> -#include <southbridge/intel/common/rcba.h> #include <southbridge/intel/bd82x6x/pch.h> #include <ec/hp/kbc1126/ec.h> diff --git a/src/mainboard/hp/revolve_810_g1/romstage.c b/src/mainboard/hp/revolve_810_g1/romstage.c index 1eea89dea1..c70660aee9 100644 --- a/src/mainboard/hp/revolve_810_g1/romstage.c +++ b/src/mainboard/hp/revolve_810_g1/romstage.c @@ -21,7 +21,6 @@ #include <arch/io.h> #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit_native.h> -#include <southbridge/intel/common/rcba.h> #include <southbridge/intel/bd82x6x/pch.h> #include <ec/hp/kbc1126/ec.h> diff --git a/src/mainboard/intel/dcp847ske/early_southbridge.c b/src/mainboard/intel/dcp847ske/early_southbridge.c index 873718fb12..f33415741f 100644 --- a/src/mainboard/intel/dcp847ske/early_southbridge.c +++ b/src/mainboard/intel/dcp847ske/early_southbridge.c @@ -23,7 +23,7 @@ #include <arch/acpi.h> #include <console/console.h> #include "northbridge/intel/sandybridge/raminit_native.h" -#include <southbridge/intel/common/rcba.h> + #include "superio.h" #include "thermal.h" diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c index 7e2241fd9e..9f46fe24e6 100644 --- a/src/mainboard/intel/emeraldlake2/romstage.c +++ b/src/mainboard/intel/emeraldlake2/romstage.c @@ -31,7 +31,6 @@ #include <northbridge/intel/sandybridge/raminit.h> #include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> -#include <southbridge/intel/common/rcba.h> #include <southbridge/intel/common/gpio.h> #include <arch/cpu.h> #include <cpu/x86/msr.h> diff --git a/src/mainboard/kontron/ktqm77/romstage.c b/src/mainboard/kontron/ktqm77/romstage.c index bff4991810..2a674a5374 100644 --- a/src/mainboard/kontron/ktqm77/romstage.c +++ b/src/mainboard/kontron/ktqm77/romstage.c @@ -29,7 +29,6 @@ #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit.h> #include <northbridge/intel/sandybridge/raminit_native.h> -#include <southbridge/intel/common/rcba.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> #include <arch/cpu.h> diff --git a/src/mainboard/lenovo/l520/romstage.c b/src/mainboard/lenovo/l520/romstage.c index de4e9f3cb4..0f6ffede3d 100644 --- a/src/mainboard/lenovo/l520/romstage.c +++ b/src/mainboard/lenovo/l520/romstage.c @@ -20,7 +20,6 @@ #include <device/pnp_def.h> #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit_native.h> -#include <southbridge/intel/common/rcba.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> diff --git a/src/mainboard/lenovo/s230u/romstage.c b/src/mainboard/lenovo/s230u/romstage.c index 83664f4ce6..b83eeaec73 100644 --- a/src/mainboard/lenovo/s230u/romstage.c +++ b/src/mainboard/lenovo/s230u/romstage.c @@ -27,7 +27,6 @@ #include <console/console.h> #include "northbridge/intel/sandybridge/sandybridge.h" #include "northbridge/intel/sandybridge/raminit_native.h" -#include <southbridge/intel/common/rcba.h> #include "southbridge/intel/bd82x6x/pch.h" #include <southbridge/intel/common/gpio.h> #include <arch/cpu.h> diff --git a/src/mainboard/lenovo/t420/romstage.c b/src/mainboard/lenovo/t420/romstage.c index bac7288d51..36e83a3c72 100644 --- a/src/mainboard/lenovo/t420/romstage.c +++ b/src/mainboard/lenovo/t420/romstage.c @@ -17,7 +17,6 @@ #include <arch/io.h> #include <northbridge/intel/sandybridge/raminit_native.h> -#include <southbridge/intel/common/rcba.h> #include <southbridge/intel/bd82x6x/pch.h> #include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h> #include <northbridge/intel/sandybridge/sandybridge.h> diff --git a/src/mainboard/lenovo/t420s/romstage.c b/src/mainboard/lenovo/t420s/romstage.c index 025a0fddba..55011cf2e2 100644 --- a/src/mainboard/lenovo/t420s/romstage.c +++ b/src/mainboard/lenovo/t420s/romstage.c @@ -19,7 +19,6 @@ #include <arch/io.h> #include <console/console.h> #include <northbridge/intel/sandybridge/raminit_native.h> -#include <southbridge/intel/common/rcba.h> #include <southbridge/intel/bd82x6x/pch.h> #include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h> #include <northbridge/intel/sandybridge/sandybridge.h> diff --git a/src/mainboard/lenovo/t430s/romstage.c b/src/mainboard/lenovo/t430s/romstage.c index 0e732ee529..3f6d9f2836 100644 --- a/src/mainboard/lenovo/t430s/romstage.c +++ b/src/mainboard/lenovo/t430s/romstage.c @@ -20,7 +20,6 @@ #include <device/pci_def.h> #include <console/console.h> #include <northbridge/intel/sandybridge/raminit_native.h> -#include <southbridge/intel/common/rcba.h> #include <southbridge/intel/bd82x6x/pch.h> void pch_enable_lpc(void) diff --git a/src/mainboard/lenovo/t520/romstage.c b/src/mainboard/lenovo/t520/romstage.c index 638e7ca67b..d7528404f8 100644 --- a/src/mainboard/lenovo/t520/romstage.c +++ b/src/mainboard/lenovo/t520/romstage.c @@ -30,7 +30,6 @@ #include <console/console.h> #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit_native.h> -#include <southbridge/intel/common/rcba.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> #include <arch/cpu.h> diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/romstage.c index 7470acc086..ba7a229a0d 100644 --- a/src/mainboard/lenovo/t530/romstage.c +++ b/src/mainboard/lenovo/t530/romstage.c @@ -21,7 +21,7 @@ #include <device/pci_def.h> #include <console/console.h> #include <northbridge/intel/sandybridge/raminit_native.h> -#include <southbridge/intel/common/rcba.h> +#include <southbridge/intel/bd82x6x/pch.h> #include <northbridge/intel/sandybridge/sandybridge.h> #include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h> #include <device/device.h> diff --git a/src/mainboard/lenovo/x201/mainboard.c b/src/mainboard/lenovo/x201/mainboard.c index 59add6851a..5d0deea263 100644 --- a/src/mainboard/lenovo/x201/mainboard.c +++ b/src/mainboard/lenovo/x201/mainboard.c @@ -21,7 +21,6 @@ #include <arch/io.h> #include <ec/acpi/ec.h> #include <northbridge/intel/nehalem/nehalem.h> -#include <southbridge/intel/common/rcba.h> #include <southbridge/intel/bd82x6x/pch.h> #include <pc80/mc146818rtc.h> diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index 1169a6ca10..d93cb8c00e 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -39,7 +39,6 @@ #include "dock.h" #include "arch/early_variables.h" -#include <southbridge/intel/common/rcba.h> #include <southbridge/intel/ibexpeak/pch.h> #include <southbridge/intel/common/gpio.h> #include <northbridge/intel/nehalem/nehalem.h> diff --git a/src/mainboard/lenovo/x220/romstage.c b/src/mainboard/lenovo/x220/romstage.c index e38dfe7e64..96e0284313 100644 --- a/src/mainboard/lenovo/x220/romstage.c +++ b/src/mainboard/lenovo/x220/romstage.c @@ -29,7 +29,6 @@ #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit.h> #include <northbridge/intel/sandybridge/raminit_native.h> -#include <southbridge/intel/common/rcba.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> #include <arch/cpu.h> diff --git a/src/mainboard/lenovo/x230/romstage.c b/src/mainboard/lenovo/x230/romstage.c index 7801d5786a..1a7decce59 100644 --- a/src/mainboard/lenovo/x230/romstage.c +++ b/src/mainboard/lenovo/x230/romstage.c @@ -30,7 +30,6 @@ #include <console/console.h> #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit_native.h> -#include <southbridge/intel/common/rcba.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> #include <arch/cpu.h> diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c index a52f153e59..3538647e3f 100644 --- a/src/mainboard/packardbell/ms2290/romstage.c +++ b/src/mainboard/packardbell/ms2290/romstage.c @@ -37,7 +37,6 @@ #include <cbmem.h> #include "arch/early_variables.h" -#include <southbridge/intel/common/rcba.h> #include <southbridge/intel/ibexpeak/pch.h> #include <northbridge/intel/nehalem/nehalem.h> diff --git a/src/mainboard/roda/rv11/romstage.c b/src/mainboard/roda/rv11/romstage.c index 6a3a56efe5..b36725c213 100644 --- a/src/mainboard/roda/rv11/romstage.c +++ b/src/mainboard/roda/rv11/romstage.c @@ -14,7 +14,6 @@ */ #include <northbridge/intel/sandybridge/sandybridge.h> -#include <southbridge/intel/common/rcba.h> #include <southbridge/intel/bd82x6x/pch.h> void mainboard_rcba_config(void) diff --git a/src/mainboard/roda/rv11/variants/rv11/romstage.c b/src/mainboard/roda/rv11/variants/rv11/romstage.c index 549167bbca..c7de994760 100644 --- a/src/mainboard/roda/rv11/variants/rv11/romstage.c +++ b/src/mainboard/roda/rv11/variants/rv11/romstage.c @@ -18,7 +18,6 @@ #include <northbridge/intel/sandybridge/raminit.h> #include <northbridge/intel/sandybridge/raminit_native.h> #include <northbridge/intel/sandybridge/sandybridge.h> -#include <southbridge/intel/common/rcba.h> #include <southbridge/intel/bd82x6x/pch.h> void pch_enable_lpc(void) diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c index 912d2c305f..cea206a02b 100644 --- a/src/mainboard/samsung/lumpy/romstage.c +++ b/src/mainboard/samsung/lumpy/romstage.c @@ -32,7 +32,6 @@ #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit.h> #include <northbridge/intel/sandybridge/raminit_native.h> -#include <southbridge/intel/common/rcba.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> #include <arch/cpu.h> @@ -103,9 +102,9 @@ void mainboard_rcba_config(void) DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); /* Enable IOAPIC (generic) */ - RCBA16(EOIC) = 0x0100; + RCBA16(OIC) = 0x0100; /* PCH BWG says to read back the IOAPIC enable register */ - (void) RCBA16(EOIC); + (void) RCBA16(OIC); } static const uint8_t *locate_spd(void) diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c index 9f1e3f6aac..f502cc393f 100644 --- a/src/mainboard/samsung/stumpy/romstage.c +++ b/src/mainboard/samsung/stumpy/romstage.c @@ -32,7 +32,6 @@ #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit.h> #include <northbridge/intel/sandybridge/raminit_native.h> -#include <southbridge/intel/common/rcba.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> #include <arch/cpu.h> @@ -112,9 +111,9 @@ void mainboard_rcba_config(void) DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); /* Enable IOAPIC (generic) */ - RCBA16(EOIC) = 0x0100; + RCBA16(OIC) = 0x0100; /* PCH BWG says to read back the IOAPIC enable register */ - (void) RCBA16(EOIC); + (void) RCBA16(OIC); } static void setup_sio_gpios(void) diff --git a/src/mainboard/sapphire/pureplatinumh61/mainboard.c b/src/mainboard/sapphire/pureplatinumh61/mainboard.c index c673294478..2267ec73ca 100644 --- a/src/mainboard/sapphire/pureplatinumh61/mainboard.c +++ b/src/mainboard/sapphire/pureplatinumh61/mainboard.c @@ -17,7 +17,6 @@ #include <device/device.h> #include <drivers/intel/gma/int15.h> #include <southbridge/intel/bd82x6x/pch.h> -#include <southbridge/intel/common/rcba.h> static void mainboard_init(struct device *dev) { diff --git a/src/mainboard/sapphire/pureplatinumh61/romstage.c b/src/mainboard/sapphire/pureplatinumh61/romstage.c index 420a956ebb..a20a1f758b 100644 --- a/src/mainboard/sapphire/pureplatinumh61/romstage.c +++ b/src/mainboard/sapphire/pureplatinumh61/romstage.c @@ -27,7 +27,6 @@ #include <console/console.h> #include "northbridge/intel/sandybridge/sandybridge.h" #include "northbridge/intel/sandybridge/raminit_native.h" -#include <southbridge/intel/common/rcba.h> #include "southbridge/intel/bd82x6x/pch.h" #include <southbridge/intel/common/gpio.h> #include <arch/cpu.h> |