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| author | Michael Niewöhner <foss@mniewoehner.de> | 2019-09-23 14:38:41 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-10-02 11:15:00 +0000 |
| commit | 6238563b2b65edac8e6dba4f8f20eb020c172317 (patch) | |
| tree | 8293ac5ef0441b978b3c447a19f8262627d25843 /src/mainboard | |
| parent | 5387144a939b4ad3d334f2b4abebb987611b0274 (diff) | |
| download | coreboot-6238563b2b65edac8e6dba4f8f20eb020c172317.tar.xz | |
soc/intel/skylake: devicetree: introduce PchHdaVcType fsp parameter
Make the the FSP Parameter PchHdaVcType a devicetree setting and make
use of it in the devicetrees of all boards that currently set it.
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: Ibafc3b6bd2495658f2bd634218042ec413a89f5e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35542
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Diffstat (limited to 'src/mainboard')
6 files changed, 5 insertions, 8 deletions
diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index 572cd6ab52..acb2a9e629 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -55,6 +55,7 @@ chip soc/intel/skylake register "PmTimerDisabled" = "0" register "EnableAzalia" = "1" register "DspEnable" = "0" + register "PchHdaVcType" = "Vc1" register "pirqa_routing" = "PCH_IRQ11" register "pirqb_routing" = "PCH_IRQ10" diff --git a/src/mainboard/asrock/h110m/ramstage.c b/src/mainboard/asrock/h110m/ramstage.c index c93e84c3d4..a247b72587 100644 --- a/src/mainboard/asrock/h110m/ramstage.c +++ b/src/mainboard/asrock/h110m/ramstage.c @@ -24,6 +24,4 @@ void mainboard_silicon_init_params(FSP_SIL_UPD *params) gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); params->CdClock = 3; - /* Enable Virtual Channel 1 */ - params->PchHdaVcType = 0x1; } diff --git a/src/mainboard/intel/kblrvp/ramstage.c b/src/mainboard/intel/kblrvp/ramstage.c index ad55c2675a..a19e96ec70 100644 --- a/src/mainboard/intel/kblrvp/ramstage.c +++ b/src/mainboard/intel/kblrvp/ramstage.c @@ -25,9 +25,6 @@ void mainboard_silicon_init_params(FSP_SIL_UPD *params) * dependencies during hardware initialization. */ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); params->CdClock = 3; - - /* Enable Virtual Channel 1 */ - params->PchHdaVcType = 0x1; } static void ioexpander_init(void *unused) diff --git a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb index 2a1cb8a021..212721a90f 100644 --- a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb @@ -30,6 +30,7 @@ chip soc/intel/skylake register "SkipExtGfxScan" = "1" register "Device4Enable" = "1" register "SaGv" = "SaGv_Enabled" + register "PchHdaVcType" = "Vc1" register "pirqa_routing" = "PCH_IRQ11" register "pirqb_routing" = "PCH_IRQ10" diff --git a/src/mainboard/supermicro/x11-lga1151-series/ramstage.c b/src/mainboard/supermicro/x11-lga1151-series/ramstage.c index 694165aefc..a16678eb33 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/ramstage.c +++ b/src/mainboard/supermicro/x11-lga1151-series/ramstage.c @@ -20,7 +20,4 @@ void mainboard_silicon_init_params(FSP_SIL_UPD *params) /* Configure pads prior to SiliconInit() in case there's any * dependencies during hardware initialization. */ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); - - /* This must be one, otherwise FSP crashes ... */ - params->PchHdaVcType = 0x1; } diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb index 1039f7a0ca..09aa8b558c 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb @@ -30,6 +30,9 @@ chip soc/intel/skylake register "PcieRpEnable[8]" = "1" register "PcieRpClkReqSupport[8]" = "0" + # FIXME: find out why FSP crashes without this + register "PchHdaVcType" = "Vc1" + device domain 0 on device pci 01.0 on end # unused device pci 01.1 on # PCIE Slot (JPCIE1) |