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authorMaxim Polyakov <max.senia.poliak@gmail.com>2019-08-21 14:47:59 +0300
committerPatrick Georgi <pgeorgi@google.com>2019-09-09 13:27:21 +0000
commit6342c93ee71ab1f33b9dfe74d45244fefc56c284 (patch)
tree310c6de6de4b403f76c9ddfc7894f513c6915be6 /src/mainboard
parenta546f11c6d5ad8970bd6022a52b1f2e6c5abab4b (diff)
downloadcoreboot-6342c93ee71ab1f33b9dfe74d45244fefc56c284.tar.xz
mb/asrock/h110m: use VR_CFG_AMP() macro to set PSI threshold
Change-Id: Iafeb7f7689a16d3b16eb0564c4dd72919a8d1382 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35068 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/asrock/h110m/devicetree.cb24
1 files changed, 12 insertions, 12 deletions
diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb
index 53705684b2..704a956119 100644
--- a/src/mainboard/asrock/h110m/devicetree.cb
+++ b/src/mainboard/asrock/h110m/devicetree.cb
@@ -95,9 +95,9 @@ chip soc/intel/skylake
# * - is set automatically for the KBL-S/KBL-DT CPUs in the vr_config.c
register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
.vr_config_enable = 1, \
- .psi1threshold = 0x50, \
- .psi2threshold = 0x10, \
- .psi3threshold = 0x4, \
+ .psi1threshold = VR_CFG_AMP(20), \
+ .psi2threshold = VR_CFG_AMP(4), \
+ .psi3threshold = VR_CFG_AMP(1), \
.psi3enable = 1, \
.psi4enable = 1, \
.imon_slope = 0x0, \
@@ -108,9 +108,9 @@ chip soc/intel/skylake
register "domain_vr_config[VR_IA_CORE]" = "{
.vr_config_enable = 1, \
- .psi1threshold = 0x50, \
- .psi2threshold = 0x14, \
- .psi3threshold = 0x4, \
+ .psi1threshold = VR_CFG_AMP(20), \
+ .psi2threshold = VR_CFG_AMP(5), \
+ .psi3threshold = VR_CFG_AMP(1), \
.psi3enable = 1, \
.psi4enable = 1, \
.imon_slope = 0x0, \
@@ -121,9 +121,9 @@ chip soc/intel/skylake
register "domain_vr_config[VR_GT_UNSLICED]" = "{
.vr_config_enable = 1, \
- .psi1threshold = 0x50, \
- .psi2threshold = 0x14, \
- .psi3threshold = 0x4, \
+ .psi1threshold = VR_CFG_AMP(20), \
+ .psi2threshold = VR_CFG_AMP(5), \
+ .psi3threshold = VR_CFG_AMP(1), \
.psi3enable = 1, \
.psi4enable = 1, \
.imon_slope = 0x0, \
@@ -134,9 +134,9 @@ chip soc/intel/skylake
register "domain_vr_config[VR_GT_SLICED]" = "{
.vr_config_enable = 1, \
- .psi1threshold = 0x50, \
- .psi2threshold = 0x14, \
- .psi3threshold = 0x4, \
+ .psi1threshold = VR_CFG_AMP(20), \
+ .psi2threshold = VR_CFG_AMP(5), \
+ .psi3threshold = VR_CFG_AMP(1), \
.psi3enable = 1, \
.psi4enable = 1, \
.imon_slope = 0x0, \