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authordavid <david_wu@quantatw.com>2015-12-09 15:39:52 +0800
committerMartin Roth <martinroth@google.com>2016-01-17 21:30:11 +0100
commit6a370748cbb39e085d949ea6855fac68cc3ec292 (patch)
tree6f5b64b4eafabcbf8a43ff25b5a91d31cfd7f3fa /src/mainboard
parent7e513d1d04ad5352844ece7cfc7b24bac57daf3a (diff)
downloadcoreboot-6a370748cbb39e085d949ea6855fac68cc3ec292.tar.xz
google/lars: Enable 20K PU on LPC_LAD 0-3
At S0, S0ix and S3 LPC LAD signals are floated at 400~500mV. BRANCH=none BUG=chrome-os-partner:48331 TEST=Build and boot on lars Change-Id: I5582007e5caaf444740fa71c9761c27614aafee2 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b855fd5834056a3f7d4aef91d634066006990a38 Original-Change-Id: I3a54f9f83f055e433cc1fea38169437ee7f9188f Original-Signed-off-by: David Wu <David_Wu@quantatw.com> Original-Reviewed-on: https://chromium-review.googlesource.com/317071 Original-Commit-Ready: David Wu <david_wu@quantatw.com> Original-Tested-by: David Wu <david_wu@quantatw.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12965 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard')
-rwxr-xr-xsrc/mainboard/google/lars/gpio.h8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/mainboard/google/lars/gpio.h b/src/mainboard/google/lars/gpio.h
index 3aebebc0aa..acb04ec01d 100755
--- a/src/mainboard/google/lars/gpio.h
+++ b/src/mainboard/google/lars/gpio.h
@@ -57,10 +57,10 @@
/* Pad configuration in ramstage. */
static const struct pad_config gpio_table[] = {
/* EC_PCH_RCIN */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
-/* LPC_LAD_0 */ PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1),
-/* LPC_LAD_1 */ PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1),
-/* LPC_LAD_2 */ PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1),
-/* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1),
+/* LPC_LAD_0 */ PAD_CFG_NF(GPP_A1, 20K_PU, DEEP, NF1),
+/* LPC_LAD_1 */ PAD_CFG_NF(GPP_A2, 20K_PU, DEEP, NF1),
+/* LPC_LAD_2 */ PAD_CFG_NF(GPP_A3, 20K_PU, DEEP, NF1),
+/* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, 20K_PU, DEEP, NF1),
/* LPC_FRAME */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
/* LPC_SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
/* PIRQA# */ /* GPP_A7 */