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authorFurquan Shaikh <furquan@google.com>2018-03-14 19:57:16 -0700
committerFurquan Shaikh <furquan@google.com>2018-03-16 04:43:01 +0000
commit6d5e10c05d99c475e63bbe95012066f9c585cfb3 (patch)
tree8cecb6956bed707c4a8900ab79c491ad87982698 /src/mainboard
parent211bb97c67ce704fb40abb6dd9971790652237e3 (diff)
downloadcoreboot-6d5e10c05d99c475e63bbe95012066f9c585cfb3.tar.xz
soc/intel/apollolake and mainboards: Use pcie_rp_clkreq_pin array
This change uses an array pcie_rp_clkreq_pin for accepting CLKREQ# from mainboards instead of defining a separate property for each root port. This allows us to use memcpy to copy the entire array into FSP params as well as new properties for PCIe root ports can be added as arrays in future CLs. BUG=b:74633273 BRANCH=reef,coral Change-Id: Ifa05f1e38fcfd95063ec327712e472cdbd12dbb7 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/25186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/reef/variants/baseboard/devicetree.cb12
-rw-r--r--src/mainboard/google/reef/variants/coral/devicetree.cb12
-rw-r--r--src/mainboard/google/reef/variants/pyro/devicetree.cb12
-rw-r--r--src/mainboard/google/reef/variants/sand/devicetree.cb12
-rw-r--r--src/mainboard/google/reef/variants/snappy/devicetree.cb12
-rw-r--r--src/mainboard/intel/apollolake_rvp/devicetree.cb12
-rw-r--r--src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb12
-rw-r--r--src/mainboard/intel/leafhill/devicetree.cb12
-rw-r--r--src/mainboard/intel/minnow3/devicetree.cb12
-rw-r--r--src/mainboard/siemens/mc_apl1/devicetree.cb12
10 files changed, 60 insertions, 60 deletions
diff --git a/src/mainboard/google/reef/variants/baseboard/devicetree.cb b/src/mainboard/google/reef/variants/baseboard/devicetree.cb
index 0f11f6366c..a8e24cdec9 100644
--- a/src/mainboard/google/reef/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/reef/variants/baseboard/devicetree.cb
@@ -4,13 +4,13 @@ chip soc/intel/apollolake
device lapic 0 on end
end
- register "pcie_rp0_clkreq_pin" = "0" # wifi/bt
+ register "pcie_rp_clkreq_pin[0]" = "0" # wifi/bt
# Disable unused clkreq of PCIe root ports
- register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED"
- register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED"
- register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED"
- register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED"
- register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"
# GPIO for PERST_0
# If the Board has PERST_0 signal, assign the GPIO
diff --git a/src/mainboard/google/reef/variants/coral/devicetree.cb b/src/mainboard/google/reef/variants/coral/devicetree.cb
index 0a06c76779..c1b7067711 100644
--- a/src/mainboard/google/reef/variants/coral/devicetree.cb
+++ b/src/mainboard/google/reef/variants/coral/devicetree.cb
@@ -4,13 +4,13 @@ chip soc/intel/apollolake
device lapic 0 on end
end
- register "pcie_rp0_clkreq_pin" = "0" # wifi/bt
+ register "pcie_rp_clkreq_pin[0]" = "0" # wifi/bt
# Disable unused clkreq of PCIe root ports
- register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED"
- register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED"
- register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED"
- register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED"
- register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"
# GPIO for PERST_0
# If the Board has PERST_0 signal, assign the GPIO
diff --git a/src/mainboard/google/reef/variants/pyro/devicetree.cb b/src/mainboard/google/reef/variants/pyro/devicetree.cb
index 5bfe2c20f0..cb297d9dce 100644
--- a/src/mainboard/google/reef/variants/pyro/devicetree.cb
+++ b/src/mainboard/google/reef/variants/pyro/devicetree.cb
@@ -4,13 +4,13 @@ chip soc/intel/apollolake
device lapic 0 on end
end
- register "pcie_rp0_clkreq_pin" = "0" # wifi/bt
+ register "pcie_rp_clkreq_pin[0]" = "0" # wifi/bt
# Disable unused clkreq of PCIe root ports
- register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED"
- register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED"
- register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED"
- register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED"
- register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"
# GPIO for PERST_0
# If the Board has PERST_0 signal, assign the GPIO
diff --git a/src/mainboard/google/reef/variants/sand/devicetree.cb b/src/mainboard/google/reef/variants/sand/devicetree.cb
index a6692e6bf7..e53af885e0 100644
--- a/src/mainboard/google/reef/variants/sand/devicetree.cb
+++ b/src/mainboard/google/reef/variants/sand/devicetree.cb
@@ -4,13 +4,13 @@ chip soc/intel/apollolake
device lapic 0 on end
end
- register "pcie_rp0_clkreq_pin" = "0" # wifi/bt
+ register "pcie_rp_clkreq_pin[0]" = "0" # wifi/bt
# Disable unused clkreq of PCIe root ports
- register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED"
- register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED"
- register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED"
- register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED"
- register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"
# GPIO for PERST_0
# If the Board has PERST_0 signal, assign the GPIO
diff --git a/src/mainboard/google/reef/variants/snappy/devicetree.cb b/src/mainboard/google/reef/variants/snappy/devicetree.cb
index 6adf94c1b3..9719368080 100644
--- a/src/mainboard/google/reef/variants/snappy/devicetree.cb
+++ b/src/mainboard/google/reef/variants/snappy/devicetree.cb
@@ -4,13 +4,13 @@ chip soc/intel/apollolake
device lapic 0 on end
end
- register "pcie_rp0_clkreq_pin" = "0" # wifi/bt
+ register "pcie_rp_clkreq_pin[0]" = "0" # wifi/bt
# Disable unused clkreq of PCIe root ports
- register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED"
- register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED"
- register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED"
- register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED"
- register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"
# GPIO for PERST_0
# If the Board has PERST_0 signal, assign the GPIO
diff --git a/src/mainboard/intel/apollolake_rvp/devicetree.cb b/src/mainboard/intel/apollolake_rvp/devicetree.cb
index 746aaf31b2..f7e82a06ca 100644
--- a/src/mainboard/intel/apollolake_rvp/devicetree.cb
+++ b/src/mainboard/intel/apollolake_rvp/devicetree.cb
@@ -1,11 +1,11 @@
chip soc/intel/apollolake
- register "pcie_rp0_clkreq_pin" = "2" # PCIe slot 2
- register "pcie_rp1_clkreq_pin" = "3" # Wifi+BT M2 slot
- register "pcie_rp2_clkreq_pin" = "0" # PCIe slot 1
- register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED"
- register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED"
- register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[0]" = "2" # PCIe slot 2
+ register "pcie_rp_clkreq_pin[1]" = "3" # Wifi+BT M2 slot
+ register "pcie_rp_clkreq_pin[2]" = "0" # PCIe slot 1
+ register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"
device cpu_cluster 0 on
device lapic 0 on end
diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb
index 45badcddbd..5a544300c0 100644
--- a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb
+++ b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb
@@ -4,13 +4,13 @@ chip soc/intel/apollolake
device lapic 0 on end
end
- register "pcie_rp0_clkreq_pin" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED"
# Disable unused clkreq of PCIe root ports
- register "pcie_rp1_clkreq_pin" = "3" # wifi/bt
- register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED"
- register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED"
- register "pcie_rp4_clkreq_pin" = "1"
- register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[1]" = "3" # wifi/bt
+ register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[4]" = "1"
+ register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"
# GPIO for PERST_0
# If the Board has PERST_0 signal, assign the GPIO
diff --git a/src/mainboard/intel/leafhill/devicetree.cb b/src/mainboard/intel/leafhill/devicetree.cb
index 2a284d2ee4..6c872b186e 100644
--- a/src/mainboard/intel/leafhill/devicetree.cb
+++ b/src/mainboard/intel/leafhill/devicetree.cb
@@ -1,11 +1,11 @@
chip soc/intel/apollolake
- register "pcie_rp0_clkreq_pin" = "CLKREQ_DISABLED"
- register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED"
- register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED"
- register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED"
- register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED"
- register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"
device cpu_cluster 0 on
device lapic 0 on end
diff --git a/src/mainboard/intel/minnow3/devicetree.cb b/src/mainboard/intel/minnow3/devicetree.cb
index 2a284d2ee4..6c872b186e 100644
--- a/src/mainboard/intel/minnow3/devicetree.cb
+++ b/src/mainboard/intel/minnow3/devicetree.cb
@@ -1,11 +1,11 @@
chip soc/intel/apollolake
- register "pcie_rp0_clkreq_pin" = "CLKREQ_DISABLED"
- register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED"
- register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED"
- register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED"
- register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED"
- register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"
device cpu_cluster 0 on
device lapic 0 on end
diff --git a/src/mainboard/siemens/mc_apl1/devicetree.cb b/src/mainboard/siemens/mc_apl1/devicetree.cb
index e2b6ceec7f..c1ef76b649 100644
--- a/src/mainboard/siemens/mc_apl1/devicetree.cb
+++ b/src/mainboard/siemens/mc_apl1/devicetree.cb
@@ -7,12 +7,12 @@ chip soc/intel/apollolake
register "sci_irq" = "SCIS_IRQ10"
# Disable unused clkreq of PCIe root ports
- register "pcie_rp0_clkreq_pin" = "3" # PCIe-PCI-Bridge
- register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED"
- register "pcie_rp2_clkreq_pin" = "0" # MACPHY
- register "pcie_rp3_clkreq_pin" = "1" # MACPHY
- register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED"
- register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[0]" = "3" # PCIe-PCI-Bridge
+ register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[2]" = "0" # MACPHY
+ register "pcie_rp_clkreq_pin[3]" = "1" # MACPHY
+ register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"
# EMMC TX DATA Delay 1
# Refer to EDS-Vol2-22.3.
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-16 00:11:14 +0000