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authorStefan Reinauer <stepan@coresystems.de>2010-07-08 16:41:05 +0000
committerStefan Reinauer <stepan@openbios.org>2010-07-08 16:41:05 +0000
commit6f57b514cb6e0598b295a3d8a4345dd42209e1e6 (patch)
treebb54404f902b1339bdba36523d4ba069628b5532 /src/mainboard
parent817d7542f708215c4128b6cdc39ca7d7e1256b26 (diff)
downloadcoreboot-6f57b514cb6e0598b295a3d8a4345dd42209e1e6.tar.xz
Fix all warnings in the tree
(does not fix the cmos.layout race yet) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5660 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/asus/m2v-mx_se/romstage.c1
-rw-r--r--src/mainboard/gigabyte/ga_2761gxdk/romstage.c3
-rw-r--r--src/mainboard/msi/ms9282/romstage.c12
3 files changed, 7 insertions, 9 deletions
diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c
index 03086ec128..cbf8ef570b 100644
--- a/src/mainboard/asus/m2v-mx_se/romstage.c
+++ b/src/mainboard/asus/m2v-mx_se/romstage.c
@@ -57,7 +57,6 @@ unsigned int get_sbdn(unsigned bus);
#include "lib/delay.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
-#include "northbridge/amd/amdk8/early_ht.c"
#include "superio/ite/it8712f/it8712f_early_serial.c"
#include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
#include "cpu/x86/mtrr/earlymtrr.c"
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
index bcead81e9e..e4762bfd09 100644
--- a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
+++ b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
@@ -123,9 +123,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */
#include "southbridge/sis/sis966/sis966_early_setup_ss.h"
-#include "southbridge/sis/sis966/sis966_early_setup_car.c"
-
-
#include "cpu/amd/car/post_cache_as_ram.c"
diff --git a/src/mainboard/msi/ms9282/romstage.c b/src/mainboard/msi/ms9282/romstage.c
index e7de603960..ed8ee85647 100644
--- a/src/mainboard/msi/ms9282/romstage.c
+++ b/src/mainboard/msi/ms9282/romstage.c
@@ -30,10 +30,11 @@
//used by raminit
#define QRANK_DIMM_SUPPORT 1
-//used by init_cpus and fidvid
-#define SET_FIDVID 1
-//if we want to wait for core1 done before DQS training, set it to 0
-#define SET_FIDVID_CORE0_ONLY 1
+// used by init_cpus and fidvid (disabled until someone tests this)
+// #define SET_FIDVID 1
+#define SET_FIDVID 0
+// if we want to wait for core1 done before DQS training, set it to 0
+// #define SET_FIDVID_CORE0_ONLY 1
#include <stdint.h>
#include <string.h>
@@ -121,7 +122,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c"
-#include "cpu/amd/model_fxx/fidvid.c"
+// Disabled until it's actually used:
+// #include "cpu/amd/model_fxx/fidvid.c"
#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"