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authorFelix Held <felix-coreboot@felixheld.de>2020-08-17 20:00:31 +0200
committerFelix Held <felix-coreboot@felixheld.de>2020-08-18 18:47:03 +0000
commit7f94b405be122b85438f4cd17aa1d43a106b987f (patch)
tree4468bc2ff805fbaa4d212f3ca7bece32189ba75b /src/mainboard
parentb69549bb07ed5f27786537fde0f1af994af98a6c (diff)
downloadcoreboot-7f94b405be122b85438f4cd17aa1d43a106b987f.tar.xz
mb/amd/mandolin: enable SoC UARTs 0 and 1 and disable 2 and 3
There are only headers for the SoC's UART 0 and 1 on the board. BUG=b:165020060 TEST=Linux only detects UART 0 and 1. Change-Id: I45929f65a5f844ae5cef792b11176f487c80766f Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44530 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb6
1 files changed, 6 insertions, 0 deletions
diff --git a/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb b/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb
index ffc18a0d69..0004ecd266 100644
--- a/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb
+++ b/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb
@@ -155,4 +155,10 @@ chip soc/amd/picasso
device pci 18.6 on end
device pci 18.7 on end
end # domain
+
+ device mmio 0xfedc9000 on end # UART0
+ device mmio 0xfedca000 on end # UART1
+ device mmio 0xfedce000 off end # UART2
+ device mmio 0xfedcf000 off end # UART3
+
end # chip soc/amd/picasso