ASUS F2A85-M: Correct and clean up PCIe config

Assign the lanes correctly to the physical slots
on the motherboard in `PlatformGnbPcie.c`.

• UMI is connected to SB via 4x PCIe bridge 8.
• The blue x16 slot is not shared with DDI and is routed
  through PCIe bridge 2.
• The black x8 slot is in fact a x4 slot and uses all 4 GPPs
  from the CPU.
• Assume that DDI is on out-of-PCIe-band lanes.

Change-Id: I44c4c83e6a8e31d6150a602a0993972ac63105bd
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3194
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-by: David Hubbard <david.c.hubbard+coreboot@gmail.com>

2 files changed, 10 insertions, 96 deletions

diff --git a/src/mainboard/asus/f2a85-m/PlatformGnbPcie.c b/src/mainboard/asus/f2a85-m/PlatformGnbPcie.c
index fff40a87f2..8ff64c6e84 100644
--- a/src/mainboard/asus/f2a85-m/PlatformGnbPcie.c
+++ b/src/mainboard/asus/f2a85-m/PlatformGnbPcie.c
@@ -72,57 +72,32 @@
  */
 
 PCIe_PORT_DESCRIPTOR PortList [] = {
-	/* PCIe port, Lanes 8:23, PCI Device Number 2 */
+	/* PCIe port, Lanes 8:23, PCI Device Number 2, blue x16 slot */
 	{
 		0, /* Descriptor flags */
 		PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 23),
 		PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
 	},
-	/* PCIe port, Lanes 16:23, PCI Device Number 3 */
+	/* PCIe port, Lanes 4:7, PCI Device Number 4, black x16 slot (in fact x4) */
 	{
 		0, /* Descriptor flags */
-		PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 16, 23),
-		PCIE_PORT_DATA_INITIALIZER (PortDisabled, ChannelTypeExt6db, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
-	},
-
-	/* PCIe port, Lanes 4, PCI Device Number 4, PCIE MINI0 */
-	{
-		0, /* Descriptor flags */
-		PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4),
+		PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 7),
 		PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
 	},
-
-	/* PCIe port, Lanes 5, PCI Device Number 5, PCIE MINI1 */
-	{
-		0, /* Descriptor flags */
-		PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5),
-		PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
-	},
-
-	/* PCIe port, Lanes 6, PCI Device Number 6, PCIE SLOT1, TODO: Disabled. */
-	{
-		0, /* Descriptor flags */
-		PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6),
-		PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
-	},
-
-	/* PCIe port, Lanes 7, PCI Device Number 7, LAN , TODO: not the last entry.*/
-	{
-		0, /* Descriptor flags  !!!IMPORTANT!!! Terminate last element of array */
-		PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7),
-		PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
-	},
-
-#if 1
-	/* Initialize Port descriptor (PCIe port, Lanes ?, PCI Device Number 8, ...) */
+	/* PCIe port, Lanes 0:3, UMI link to SB, PCI Device Number 8 */
 	{
 		DESCRIPTOR_TERMINATE_LIST, /* Descriptor flags  !!!IMPORTANT!!! Terminate last element of array */
 		PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3),
 		PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
 	},
-#endif
 };
 
+/*
+ * It is not known, if the setup is complete.
+ *
+ * Tested and works: VGA/DVI
+ * Untested: HDMI
+ */
 PCIe_DDI_DESCRIPTOR DdiList [] = {
 	// DP0 to HDMI0/DP
 	{
@@ -139,29 +114,9 @@ PCIe_DDI_DESCRIPTOR DdiList [] = {
 	// DP2 to HDMI1/DP
 	{
 		0,
-//    PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 32, 38),
 		PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 32, 35),
-		//PCIE_DDI_DATA_INITIALIZER (ConnectorTypeEDP, Aux3, Hdp3)
 		PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux3, Hdp3)
 	},
-	// GFX Lane 15-12
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 12, 15),
-		PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux4, Hdp4)
-	},
-	// GFX Lane 11-8
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 16, 19),
-		PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux5, Hdp5)
-	},
-	// GFX Lane 7-4
-	{
-		DESCRIPTOR_TERMINATE_LIST,
-		PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 20, 23),
-		PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux6, Hdp6)
-	}
 };
 
 PCIe_COMPLEX_DESCRIPTOR Trinity = {
@@ -205,7 +160,6 @@ OemCustomizeInitEarly (
 	// Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
 	//
 	AllocHeapParams.RequestedBufferSize = sizeof(Trinity) + sizeof(PortList) + sizeof(DdiList);
-
 	AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
 	AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
 	Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
diff --git a/src/mainboard/asus/f2a85-m/PlatformGnbPcieComplex.h b/src/mainboard/asus/f2a85-m/PlatformGnbPcieComplex.h
index 3f14805b7c..b3c69cfc9b 100644
--- a/src/mainboard/asus/f2a85-m/PlatformGnbPcieComplex.h
+++ b/src/mainboard/asus/f2a85-m/PlatformGnbPcieComplex.h
@@ -24,46 +24,6 @@
 #include "AGESA.h"
 #include "amdlib.h"
 
-//GNB GPP Port4
-#define GNB_GPP_PORT4_PORT_PRESENT      1  //0:Disable 1:Enable
-#define GNB_GPP_PORT4_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
-#define GNB_GPP_PORT4_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT4_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
-                                           //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
-#define GNB_GPP_PORT4_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
-
-//GNB GPP Port5
-#define GNB_GPP_PORT5_PORT_PRESENT      1  //0:Disable 1:Enable
-#define GNB_GPP_PORT5_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
-#define GNB_GPP_PORT5_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT5_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
-                                           //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
-#define GNB_GPP_PORT5_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
-
-//GNB GPP Port6
-#define GNB_GPP_PORT6_PORT_PRESENT      1  //0:Disable 1:Enable
-#define GNB_GPP_PORT6_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
-#define GNB_GPP_PORT6_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT6_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
-                                           //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
-#define GNB_GPP_PORT6_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
-
-//GNB GPP Port7
-#define GNB_GPP_PORT7_PORT_PRESENT      1  //0:Disable 1:Enable
-#define GNB_GPP_PORT7_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
-#define GNB_GPP_PORT7_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT7_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
-                                           //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
-#define GNB_GPP_PORT7_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
-
-//GNB GPP Port8
-#define GNB_GPP_PORT8_PORT_PRESENT      1  //0:Disable 1:Enable
-#define GNB_GPP_PORT8_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
-#define GNB_GPP_PORT8_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT8_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
-                                           //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
-#define GNB_GPP_PORT8_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
-
 VOID
 OemCustomizeInitEarly (
   IN  OUT AMD_EARLY_PARAMS    *InitEarly