diff options
| author | Kane Chen <kane.chen@intel.com> | 2015-10-26 15:11:53 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2016-01-22 14:16:23 +0100 |
| commit | 8ff4308243bba649f83f73fa0973358e46e9599f (patch) | |
| tree | c76bfd7d82fee345081d965b63e0cce3d8a51023 /src/mainboard | |
| parent | 530e1f7455de8c5dbd3e4f12fa77b0d6cf8be69f (diff) | |
| download | coreboot-8ff4308243bba649f83f73fa0973358e46e9599f.tar.xz | |
intel/strago: Set POWER_SOURCE_CONFIG in devicetree.cb
SVID config set to SVID_PMIC_CONFIG
BUG=none
BRANCH=none
TEST=build, boot to OS and check the register is set properly
Change-Id: If63b8112d4da0347c3a2c4c6d82b12a1f618291c
Signed-off-by: Kane Chen <kane.chen@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/308576
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13117
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard')
| -rwxr-xr-x | src/mainboard/intel/strago/devicetree.cb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/intel/strago/devicetree.cb b/src/mainboard/intel/strago/devicetree.cb index bcf92f1c49..788153a44a 100755 --- a/src/mainboard/intel/strago/devicetree.cb +++ b/src/mainboard/intel/strago/devicetree.cb @@ -34,7 +34,7 @@ chip soc/intel/braswell register "PcdEnableI2C5" = "1" register "PcdEnableI2C6" = "1" register "PunitPwrConfigDisable" = "0" # Enable SVID - register "ChvSvidConfig" = "SVID_CONFIG1" + register "ChvSvidConfig" = "SVID_PMIC_CONFIG" register "PcdEmmcMode" = "PCH_ACPI_MODE" register "PcdUsb3ClkSsc" = "1" register "PcdDispClkSsc" = "1" |