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authorBrandon Breitenstein <brandon.breitenstein@intel.com>2020-03-11 16:16:16 -0700
committerPatrick Georgi <pgeorgi@google.com>2020-03-30 08:41:37 +0000
commit91dddd47b3e5a34124e34222ab3f2a1f00ce9246 (patch)
tree3ff01ea023a54ec138520373656a3d16c0991354 /src/mainboard
parentfc932374a2860addbdf00dc3bd141b556508b8f3 (diff)
downloadcoreboot-91dddd47b3e5a34124e34222ab3f2a1f00ce9246.tar.xz
tgl boards: Configure retimer Aux orientation
In order to create a working baseline all ports are being set to have retimers. Setting the TcssAuxOri UPD to 0 in order for the SoC to not misconfigure the ports. Volteer will need some additional changes after this is implemented to account for ports that do not have a retimer. This setting is in the process of being documented in the TGL EDS and we can update once it is fully understood what this setting is changing on the SOC side. BUG=b:145943811 BRANCH=none TEST=Boot to OS and check Type-C port1 Display on Volteer, Connecting Type-c display should work regardless of Type-c cable orientation. Change-Id: I29eb0513299126ad8d1ee11ded2c771f28ad13f3 Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39460 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/volteer/variants/baseboard/devicetree.cb1
-rw-r--r--src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb3
-rw-r--r--src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb3
3 files changed, 7 insertions, 0 deletions
diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
index 6be69fe2ee..361e563cab 100644
--- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
@@ -127,6 +127,7 @@ chip soc/intel/tigerlake
# TCSS USB3
register "TcssXhciEn" = "1"
+ register "TcssAuxOri" = "0"
# DP port
register "DdiPortAConfig" = "1" # eDP
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
index 8fd9087c7f..6cef4f84a6 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
@@ -103,6 +103,9 @@ chip soc/intel/tigerlake
[PchSerialIoIndexUART2] = PchSerialIoPci,
}"
+ # TCSS USB3
+ register "TcssAuxOri" = "0"
+
#HD Audio
register "PchHdaDspEnable" = "1"
register "PchHdaAudioLinkHdaEnable" = "0"
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
index 4ff35cc437..c5cc800224 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
@@ -99,6 +99,9 @@ chip soc/intel/tigerlake
[PchSerialIoIndexUART2] = PchSerialIoPci,
}"
+ # TCSS USB3
+ register "TcssAuxOri" = "0"
+
#HD Audio
register "PchHdaDspEnable" = "1"
register "PchHdaAudioLinkHdaEnable" = "0"