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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2013-12-23 09:56:36 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2013-12-30 07:15:27 +0100 |
| commit | b316585eaf3dbaa14c3f8ccb704dd2e0d37ed5ea (patch) | |
| tree | aa0e5d4e8e20200f2ec3a305ad51ba1ec98136fd /src/mainboard | |
| parent | 0946190e15f7aed3fdad5a60ef76cb1c6051c69c (diff) | |
| download | coreboot-b316585eaf3dbaa14c3f8ccb704dd2e0d37ed5ea.tar.xz | |
AMD K8 (pre-F): Clean platforms without K8_REV_F_SUPPORT
Change-Id: Ie109f58bd8ce54754b8d0b00118e75ace8717df0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4566
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/hp/dl145_g1/romstage.c | 3 | ||||
| -rw-r--r-- | src/mainboard/iwill/dk8_htx/romstage.c | 7 | ||||
| -rw-r--r-- | src/mainboard/iwill/dk8s2/romstage.c | 7 | ||||
| -rw-r--r-- | src/mainboard/iwill/dk8x/romstage.c | 7 |
4 files changed, 0 insertions, 24 deletions
diff --git a/src/mainboard/hp/dl145_g1/romstage.c b/src/mainboard/hp/dl145_g1/romstage.c index 87f93e886f..67ce9c1f01 100644 --- a/src/mainboard/hp/dl145_g1/romstage.c +++ b/src/mainboard/hp/dl145_g1/romstage.c @@ -117,9 +117,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) setup_dl145g1_resource_map(); //setup_default_resource_map(); -#if CONFIG_MEM_TRAIN_SEQ == 1 - set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram -#endif setup_coherent_ht_domain(); wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS diff --git a/src/mainboard/iwill/dk8_htx/romstage.c b/src/mainboard/iwill/dk8_htx/romstage.c index 5009829c1f..070fb0700c 100644 --- a/src/mainboard/iwill/dk8_htx/romstage.c +++ b/src/mainboard/iwill/dk8_htx/romstage.c @@ -1,7 +1,3 @@ -#if CONFIG_K8_REV_F_SUPPORT -#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 -#endif - #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -98,9 +94,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n"); -#if CONFIG_MEM_TRAIN_SEQ == 1 - set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram -#endif setup_coherent_ht_domain(); // routing table and start other core0 wait_all_core0_started(); diff --git a/src/mainboard/iwill/dk8s2/romstage.c b/src/mainboard/iwill/dk8s2/romstage.c index e1d8bf1103..7c8d4a5e59 100644 --- a/src/mainboard/iwill/dk8s2/romstage.c +++ b/src/mainboard/iwill/dk8s2/romstage.c @@ -1,7 +1,3 @@ -#if CONFIG_K8_REV_F_SUPPORT -#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 -#endif - #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -99,9 +95,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n"); -#if CONFIG_MEM_TRAIN_SEQ == 1 - set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram -#endif setup_coherent_ht_domain(); // routing table and start other core0 wait_all_core0_started(); diff --git a/src/mainboard/iwill/dk8x/romstage.c b/src/mainboard/iwill/dk8x/romstage.c index f4147d2145..b5a1d71b03 100644 --- a/src/mainboard/iwill/dk8x/romstage.c +++ b/src/mainboard/iwill/dk8x/romstage.c @@ -1,7 +1,3 @@ -#if CONFIG_K8_REV_F_SUPPORT -#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 -#endif - #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -99,9 +95,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n"); -#if CONFIG_MEM_TRAIN_SEQ == 1 - set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram -#endif setup_coherent_ht_domain(); // routing table and start other core0 wait_all_core0_started(); |