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authorKarthikeyan Ramasubramanian <kramasub@google.com>2020-02-07 13:11:02 -0700
committerPatrick Georgi <pgeorgi@google.com>2020-02-09 19:29:15 +0000
commitcc633f2e3a946e3538f71e9e9918183f8f40015e (patch)
tree2996b235bd8811d27f33b68bf2f4b509d3a50c14 /src/mainboard
parent118e9755ecbd5dc8f793db620df228c47d850707 (diff)
downloadcoreboot-cc633f2e3a946e3538f71e9e9918183f8f40015e.tar.xz
mb/google/dedede: Add GPE configuration
Configure the GPIO groups to be routed to the GPE0 block. BUG=None TEST=Build the mainboard. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Ife4d0179bd9fe1785e971686478f7c76de805e87 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/dedede/variants/baseboard/devicetree.cb16
1 files changed, 16 insertions, 0 deletions
diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
index cdd325cdd6..aedd32f7cc 100644
--- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
@@ -3,6 +3,22 @@ chip soc/intel/tigerlake
device lapic 0 on end
end
+ # GPE configuration
+ # Note that GPE events called out in ASL code rely on this
+ # route, i.e., if this route changes then the affected GPE
+ # offset bits also need to be changed.
+ # DW0 is used by:
+ # - GPP_B3 - TRACKPAD_INT_ODL
+ # - GPP_B4 - H1_AP_INT_ODL
+ # DW1 is used by:
+ # - GPP_D3 - WLAN_PCIE_WAKE_ODL
+ # DW2 is used by:
+ # - GPP_H16 - WWAN_HOST_WAKE
+ # EC_AP_WAKE_ODL is routed to LAN_WAKE#/GPD02 & is part of DW3.
+ register "pmc_gpe0_dw0" = "GPP_B"
+ register "pmc_gpe0_dw1" = "GPP_D"
+ register "pmc_gpe0_dw2" = "GPP_H"
+
device domain 0 on
device pci 00.0 off end # Host Bridge
device pci 02.0 off end # Integrated Graphics Device