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authorMarc Jones <marcj303@gmail.com>2017-08-07 19:08:24 -0600
committerMarc Jones <marc@marcjonesconsulting.com>2017-08-14 14:50:51 +0000
commitdfeb1c4da9be7ac97bd31f580ff2fff0c4b3256e (patch)
tree40af1e9b65705e3886408d07e1faaba85949bd1f /src/mainboard
parent4b7b18d14ac99d2337796facd3028647799b4f66 (diff)
downloadcoreboot-dfeb1c4da9be7ac97bd31f580ff2fff0c4b3256e.tar.xz
stoneyridge: Rename hudson to southbridge
Simplify funciton names and remove reference to hudson in stoneyridge. The southbridge in Stoney Ridge is Kern and hudson naming is no longer accurate. BUG=b:62200157 BRANCH=none TEST=Build and booted on Kahlee. Change-Id: Ide7a72dae69b881997101f1e37a1ac739901744d Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/20912 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/amd/gardenia/BiosCallOuts.c2
-rw-r--r--src/mainboard/amd/gardenia/bootblock/BiosCallOuts.c6
-rw-r--r--src/mainboard/amd/gardenia/mptable.c2
-rw-r--r--src/mainboard/google/kahlee/BiosCallOuts.c2
-rw-r--r--src/mainboard/google/kahlee/bootblock/BiosCallOuts.c6
-rw-r--r--src/mainboard/google/kahlee/bootblock/bootblock.c4
-rw-r--r--src/mainboard/google/kahlee/ec.c2
-rw-r--r--src/mainboard/google/kahlee/gpio.c2
-rw-r--r--src/mainboard/google/kahlee/mptable.c2
9 files changed, 14 insertions, 14 deletions
diff --git a/src/mainboard/amd/gardenia/BiosCallOuts.c b/src/mainboard/amd/gardenia/BiosCallOuts.c
index fd03f4e3fa..31681cbe27 100644
--- a/src/mainboard/amd/gardenia/BiosCallOuts.c
+++ b/src/mainboard/amd/gardenia/BiosCallOuts.c
@@ -17,7 +17,7 @@
#include <BiosCallOuts.h>
#include <FchPlatform.h>
#include <soc/imc.h>
-#include <soc/hudson.h>
+#include <soc/southbridge.h>
#include <stdlib.h>
static AGESA_STATUS fch_initenv(UINT32 Func, UINTN FchData, VOID *ConfigPtr)
diff --git a/src/mainboard/amd/gardenia/bootblock/BiosCallOuts.c b/src/mainboard/amd/gardenia/bootblock/BiosCallOuts.c
index a54078a283..b0a3e23ff8 100644
--- a/src/mainboard/amd/gardenia/bootblock/BiosCallOuts.c
+++ b/src/mainboard/amd/gardenia/bootblock/BiosCallOuts.c
@@ -16,7 +16,7 @@
#include <AGESA.h>
#include <BiosCallOuts.h>
#include <FchPlatform.h>
-#include <soc/hudson.h>
+#include <soc/southbridge.h>
#include <stdlib.h>
static const GPIO_CONTROL oem_gardenia_gpio[] = {
@@ -53,8 +53,8 @@ static AGESA_STATUS fch_initreset(UINT32 Func, UINTN FchData, VOID *ConfigPtr)
FCH_RESET_DATA_BLOCK *FchParams_reset;
FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData;
printk(BIOS_DEBUG, "Fch OEM config in INIT RESET ");
- FchParams_reset->FchReset.SataEnable = hudson_sata_enable();
- FchParams_reset->FchReset.IdeEnable = hudson_ide_enable();
+ FchParams_reset->FchReset.SataEnable = sb_sata_enable();
+ FchParams_reset->FchReset.IdeEnable = sb_ide_enable();
FchParams_reset->EarlyOemGpioTable = oem_gardenia_gpio;
printk(BIOS_DEBUG, "Done\n");
}
diff --git a/src/mainboard/amd/gardenia/mptable.c b/src/mainboard/amd/gardenia/mptable.c
index f32b8dad89..c32955866e 100644
--- a/src/mainboard/amd/gardenia/mptable.c
+++ b/src/mainboard/amd/gardenia/mptable.c
@@ -23,7 +23,7 @@
#include <cpu/amd/amdfam15.h>
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
-#include <soc/hudson.h>
+#include <soc/southbridge.h>
#include <amd_pci_util.h>
static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
diff --git a/src/mainboard/google/kahlee/BiosCallOuts.c b/src/mainboard/google/kahlee/BiosCallOuts.c
index e6c26ee5cc..f651876eeb 100644
--- a/src/mainboard/google/kahlee/BiosCallOuts.c
+++ b/src/mainboard/google/kahlee/BiosCallOuts.c
@@ -16,7 +16,7 @@
#include <AGESA.h>
#include <BiosCallOuts.h>
#include <FchPlatform.h>
-#include <soc/hudson.h>
+#include <soc/southbridge.h>
#include <stdlib.h>
extern const GPIO_CONTROL oem_kahlee_gpio[];
diff --git a/src/mainboard/google/kahlee/bootblock/BiosCallOuts.c b/src/mainboard/google/kahlee/bootblock/BiosCallOuts.c
index b70db1dc0e..162fc50826 100644
--- a/src/mainboard/google/kahlee/bootblock/BiosCallOuts.c
+++ b/src/mainboard/google/kahlee/bootblock/BiosCallOuts.c
@@ -16,7 +16,7 @@
#include <AGESA.h>
#include <BiosCallOuts.h>
#include <FchPlatform.h>
-#include <soc/hudson.h>
+#include <soc/southbridge.h>
#include <stdlib.h>
extern const GPIO_CONTROL oem_kahlee_gpio[];
@@ -29,8 +29,8 @@ static AGESA_STATUS fch_initreset(UINT32 Func, UINTN FchData, VOID *ConfigPtr)
FCH_RESET_DATA_BLOCK *FchParams_reset;
FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData;
printk(BIOS_DEBUG, "Fch OEM config in INIT RESET ");
- FchParams_reset->FchReset.SataEnable = hudson_sata_enable();
- FchParams_reset->FchReset.IdeEnable = hudson_ide_enable();
+ FchParams_reset->FchReset.SataEnable = sb_sata_enable();
+ FchParams_reset->FchReset.IdeEnable = sb_ide_enable();
FchParams_reset->EarlyOemGpioTable = oem_kahlee_gpio;
printk(BIOS_DEBUG, "Done\n");
}
diff --git a/src/mainboard/google/kahlee/bootblock/bootblock.c b/src/mainboard/google/kahlee/bootblock/bootblock.c
index caa24d5254..3041a8fbec 100644
--- a/src/mainboard/google/kahlee/bootblock/bootblock.c
+++ b/src/mainboard/google/kahlee/bootblock/bootblock.c
@@ -15,7 +15,7 @@
#include <bootblock_common.h>
#include <ec.h>
-#include <soc/hudson.h>
+#include <soc/southbridge.h>
void bootblock_mainboard_init(void)
{
@@ -23,5 +23,5 @@ void bootblock_mainboard_init(void)
mainboard_ec_init();
/* Setup TPM decode before verstage */
- hudson_tpm_decode_spi();
+ sb_tpm_decode_spi();
}
diff --git a/src/mainboard/google/kahlee/ec.c b/src/mainboard/google/kahlee/ec.c
index 71c6e1023c..75ed1fa8eb 100644
--- a/src/mainboard/google/kahlee/ec.c
+++ b/src/mainboard/google/kahlee/ec.c
@@ -18,7 +18,7 @@
#include <ec/google/chromeec/ec.h>
#include "ec.h"
#include <rules.h>
-#include <soc/hudson.h>
+#include <soc/southbridge.h>
static void ramstage_ec_init(void)
{
diff --git a/src/mainboard/google/kahlee/gpio.c b/src/mainboard/google/kahlee/gpio.c
index 56a5e3d2c7..b815ac3d6b 100644
--- a/src/mainboard/google/kahlee/gpio.c
+++ b/src/mainboard/google/kahlee/gpio.c
@@ -15,7 +15,7 @@
#include <AGESA.h>
#include <FchPlatform.h>
-#include <soc/hudson.h>
+#include <soc/southbridge.h>
#include <stdlib.h>
const GPIO_CONTROL oem_kahlee_gpio[] = {
diff --git a/src/mainboard/google/kahlee/mptable.c b/src/mainboard/google/kahlee/mptable.c
index f32b8dad89..c32955866e 100644
--- a/src/mainboard/google/kahlee/mptable.c
+++ b/src/mainboard/google/kahlee/mptable.c
@@ -23,7 +23,7 @@
#include <cpu/amd/amdfam15.h>
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
-#include <soc/hudson.h>
+#include <soc/southbridge.h>
#include <amd_pci_util.h>
static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)