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authorMike Banon <mikebdp2@gmail.com>2020-02-13 15:34:24 +0000
committerPatrick Georgi <pgeorgi@google.com>2020-02-24 13:54:41 +0000
commite3229a5192a84c04a4d1f0307d8cfb5e864b7ff3 (patch)
treef5de182e8349580f39f55c0e4adbbec754a1bc45 /src/mainboard
parent44db2f60121d90c1829b66523357c26b9a9bf358 (diff)
downloadcoreboot-e3229a5192a84c04a4d1f0307d8cfb5e864b7ff3.tar.xz
mb/amd/olivehill: Switch away from ROMCC_BOOTBLOCK
Warning: not tested on hardware. Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: If8dd531db4a4a16ad7a068ceb281a01f4f245386 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38867 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/amd/olivehill/Kconfig4
-rw-r--r--src/mainboard/amd/olivehill/Kconfig.name4
-rw-r--r--src/mainboard/amd/olivehill/Makefile.inc2
-rw-r--r--src/mainboard/amd/olivehill/bootblock.c (renamed from src/mainboard/amd/olivehill/romstage.c)25
4 files changed, 8 insertions, 27 deletions
diff --git a/src/mainboard/amd/olivehill/Kconfig b/src/mainboard/amd/olivehill/Kconfig
index 78f768f132..bd3dd9384c 100644
--- a/src/mainboard/amd/olivehill/Kconfig
+++ b/src/mainboard/amd/olivehill/Kconfig
@@ -13,14 +13,10 @@
# GNU General Public License for more details.
#
-config BOARD_AMD_OLIVEHILL
- def_bool n
-
if BOARD_AMD_OLIVEHILL
config BOARD_SPECIFIC_OPTIONS
def_bool y
- #select ROMCC_BOOTBLOCK
select CPU_AMD_AGESA_FAMILY16_KB
select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB
select SOUTHBRIDGE_AMD_AGESA_YANGTZE
diff --git a/src/mainboard/amd/olivehill/Kconfig.name b/src/mainboard/amd/olivehill/Kconfig.name
index d065472731..fd1a713aac 100644
--- a/src/mainboard/amd/olivehill/Kconfig.name
+++ b/src/mainboard/amd/olivehill/Kconfig.name
@@ -1,2 +1,2 @@
-#config BOARD_AMD_OLIVEHILL
-# bool"Olive Hill"
+config BOARD_AMD_OLIVEHILL
+ bool "Olive Hill"
diff --git a/src/mainboard/amd/olivehill/Makefile.inc b/src/mainboard/amd/olivehill/Makefile.inc
index f8895faa92..4dde2cfd1e 100644
--- a/src/mainboard/amd/olivehill/Makefile.inc
+++ b/src/mainboard/amd/olivehill/Makefile.inc
@@ -13,6 +13,8 @@
# GNU General Public License for more details.
#
+bootblock-y += bootblock.c
+
romstage-y += buildOpts.c
romstage-y += BiosCallOuts.c
romstage-y += OemCustomize.c
diff --git a/src/mainboard/amd/olivehill/romstage.c b/src/mainboard/amd/olivehill/bootblock.c
index dfe7c49f9f..d1f8d606e4 100644
--- a/src/mainboard/amd/olivehill/romstage.c
+++ b/src/mainboard/amd/olivehill/bootblock.c
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
@@ -13,32 +11,17 @@
* GNU General Public License for more details.
*/
-#include <stdint.h>
#include <amdblocks/acpimmio.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pci_ops.h>
-#include <northbridge/amd/agesa/state_machine.h>
-#include <southbridge/amd/agesa/hudson/hudson.h>
+#include <bootblock_common.h>
+#include <device/pnp_ops.h>
-void board_BeforeAgesa(struct sysinfo *cb)
+void bootblock_mainboard_early_init(void)
{
int i;
u32 val;
- /* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
- * LpcClk[1:0]". To be consistent with Parmer, setting to 4mA
- * even though the register is not documented in the Kabini BKDG.
- * Otherwise the serial output is bad code.
- */
- pm_io_write8(0xd2, 0);
-
/* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */
- pm_io_write8(0xea, 1);
-
- /* Set LPC decode enables. */
- pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
- pci_write_config32(dev, 0x44, 0xff03ffd5);
+ pm_write8(0xea, 0x1);
/* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */
for (i = 0; i < 200000; i++)