diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2014-08-06 15:27:12 -0500 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-03-26 00:26:42 +0100 |
| commit | e68ee3b6a3bbf74ec971a3b2a230a59c1944da91 (patch) | |
| tree | 4accff9ffa20ea75aaedcac67a110bda1e80631e /src/mainboard | |
| parent | 8385cdf10bdded43fc76a96544b567f51f1d197e (diff) | |
| download | coreboot-e68ee3b6a3bbf74ec971a3b2a230a59c1944da91.tar.xz | |
tegra132: move common bootblock init into SoC code
The current 2 boards were setting up clocks and enabling
peripherals that apply to the SoC generically. Therefore,
move the common pieces into the SoC code.
BUG=chrome-os-partner:31105
BRANCH=None
TEST=Built and booted through depthcharge on ryu.
Change-Id: I94ed4b5cc4fafee508d86eefe44cf3ba6f65dc3b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6dad573c8689b79bb4aa615811a10f44e7d8c809
Original-Change-Id: I6df1813f88362b8beaf1a716f4f92e42e4b73406
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/211191
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-on: http://review.coreboot.org/8917
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/rush/bootblock.c | 11 | ||||
| -rw-r--r-- | src/mainboard/google/rush_ryu/bootblock.c | 9 |
2 files changed, 8 insertions, 12 deletions
diff --git a/src/mainboard/google/rush/bootblock.c b/src/mainboard/google/rush/bootblock.c index 4df915edf9..17372bd86d 100644 --- a/src/mainboard/google/rush/bootblock.c +++ b/src/mainboard/google/rush/bootblock.c @@ -33,8 +33,8 @@ static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE; static const struct pad_config uart_console_pads[] = { - /* Hard coded pad usage for UARTA. */ - PAD_CFG_SFIO(KB_ROW9, 0, UA3), + /* UARTA: tx and rx. */ + PAD_CFG_SFIO(KB_ROW9, PINMUX_PULL_NONE, UA3), PAD_CFG_SFIO(KB_ROW10, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, UA3), /* * Disable UART2 pads as they are default connected to UARTA controller. @@ -71,8 +71,6 @@ static void set_clock_sources(void) /* UARTA gets PLLP, deactivate CLK_UART_DIV_OVERRIDE */ writel(PLLP << CLK_SOURCE_SHIFT, &clk_rst->clk_src_uarta); - clock_configure_source(mselect, PLLP, 102000); - /* The PMIC is on I2C5 and can run at 400 KHz. */ clock_configure_i2c_scl_freq(i2c5, PLLP, 400); @@ -85,9 +83,8 @@ void bootblock_mainboard_init(void) { set_clock_sources(); - clock_enable_clear_reset(CLK_L_CACHE2 | CLK_L_TMR, - CLK_H_I2C5 | CLK_H_APBDMA, - 0, CLK_V_MSELECT, 0, 0); + /* Enable PMIC I2C controller. */ + clock_enable_clear_reset(0, CLK_H_I2C5, 0, 0, 0, 0); /* Set up the pads required to load romstage. */ soc_configure_pads(padcfgs, ARRAY_SIZE(padcfgs)); diff --git a/src/mainboard/google/rush_ryu/bootblock.c b/src/mainboard/google/rush_ryu/bootblock.c index a9de44ade1..e5975d2dbc 100644 --- a/src/mainboard/google/rush_ryu/bootblock.c +++ b/src/mainboard/google/rush_ryu/bootblock.c @@ -33,8 +33,8 @@ static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE; static const struct pad_config uart_console_pads[] = { - /* Hard coded pad usage for UARTA. */ - PAD_CFG_SFIO(KB_ROW9, 0, UA3), + /* UARTA: tx and rx. */ + PAD_CFG_SFIO(KB_ROW9, PINMUX_PULL_NONE, UA3), PAD_CFG_SFIO(KB_ROW10, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, UA3), /* * Disable UART2 pads as they are default connected to UARTA controller. @@ -83,9 +83,8 @@ void bootblock_mainboard_init(void) { set_clock_sources(); - clock_enable_clear_reset(CLK_L_CACHE2 | CLK_L_TMR, - CLK_H_I2C5 | CLK_H_APBDMA, - 0, CLK_V_MSELECT, 0, 0); + /* Enable PMIC I2C controller. */ + clock_enable_clear_reset(0, CLK_H_I2C5, 0, 0, 0, 0); /* Set up the pads required to load romstage. */ soc_configure_pads(padcfgs, ARRAY_SIZE(padcfgs)); |