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authorWisley Chen <wisley.chen@quanta.corp-partner.google.com>2020-01-06 17:44:10 +0800
committerShelley Chen <shchen@google.com>2020-02-06 03:48:21 +0000
commiteae254efb324e89d30d0f6abd3e40d6e951abba9 (patch)
tree1ec6965c683818e8f4325bfb4a94ed2819ad1673 /src/mainboard
parenta547584445c086fdcd0833bbbe649a11019fcd11 (diff)
downloadcoreboot-eae254efb324e89d30d0f6abd3e40d6e951abba9.tar.xz
mb/google/hatch: Add noise mitigation setting for dratini/jinlon
Enable acoustic noise mitigation, the slow slew rates are fast time divided by 8 and disable Fast PKG C State Ramp (IA, GT, SA). BRANCH=hatch BUG=b:143501884 TEST=build and verify that noise reduce. Change-Id: I65f47288a7b1da98296fdba87ab5ca0c3a567aaf Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38212 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/hatch/variants/dratini/overridetree.cb9
-rw-r--r--src/mainboard/google/hatch/variants/jinlon/overridetree.cb9
2 files changed, 18 insertions, 0 deletions
diff --git a/src/mainboard/google/hatch/variants/dratini/overridetree.cb b/src/mainboard/google/hatch/variants/dratini/overridetree.cb
index f820629198..5c30a5a93f 100644
--- a/src/mainboard/google/hatch/variants/dratini/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/dratini/overridetree.cb
@@ -17,6 +17,15 @@ chip soc/intel/cannonlake
[PchSerialIoIndexUART2] = PchSerialIoDisabled,
}"
+ # VR Slew rate setting
+ register "AcousticNoiseMitigation" = "1"
+ register "SlowSlewRateForIa" = "2"
+ register "SlowSlewRateForGt" = "2"
+ register "SlowSlewRateForSa" = "2"
+ register "FastPkgCRampDisableIa" = "1"
+ register "FastPkgCRampDisableGt" = "1"
+ register "FastPkgCRampDisableSa" = "1"
+
# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |
diff --git a/src/mainboard/google/hatch/variants/jinlon/overridetree.cb b/src/mainboard/google/hatch/variants/jinlon/overridetree.cb
index c9613d2677..f3f6c3b949 100644
--- a/src/mainboard/google/hatch/variants/jinlon/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/jinlon/overridetree.cb
@@ -17,6 +17,15 @@ chip soc/intel/cannonlake
[PchSerialIoIndexUART2] = PchSerialIoDisabled,
}"
+ # VR Slew rate setting
+ register "AcousticNoiseMitigation" = "1"
+ register "SlowSlewRateForIa" = "2"
+ register "SlowSlewRateForGt" = "2"
+ register "SlowSlewRateForSa" = "2"
+ register "FastPkgCRampDisableIa" = "1"
+ register "FastPkgCRampDisableGt" = "1"
+ register "FastPkgCRampDisableSa" = "1"
+
# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |