Intel sch board & chip: Remove - using LATE_CBMEM_INIT

All boards and chips that are still using LATE_CBMEM_INIT are being
removed as previously discussed.

If these boards and chips are updated to not use LATE_CBMEM_INIT, they
can be restored to the active codebase from the 4.7 branch.

chips:
soc/intel/sch

Mainboards:
mainboard/iwave/iWRainbowG6

Change-Id: Ida0570988a23fd0d13c6fcbe54f94ab0668c9eae
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/22027
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

24 files changed, 0 insertions, 1610 deletions

diff --git a/src/mainboard/iwave/Kconfig b/src/mainboard/iwave/Kconfig
deleted file mode 100644
index 2af87f9abc..0000000000
--- a/src/mainboard/iwave/Kconfig
+++ /dev/null
@@ -1,17 +0,0 @@
-if VENDOR_IWAVE
-
-choice
-	prompt "Mainboard model"
-	depends on VENDOR_IWAVE
-
-source "src/mainboard/iwave/*/Kconfig.name"
-
-endchoice
-
-source "src/mainboard/iwave/*/Kconfig"
-
-config MAINBOARD_VENDOR
-	string
-	default "iWave"
-
-endif # VENDOR_IWAVE
diff --git a/src/mainboard/iwave/Kconfig.name b/src/mainboard/iwave/Kconfig.name
deleted file mode 100644
index 2babae31dd..0000000000
--- a/src/mainboard/iwave/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config VENDOR_IWAVE
-	bool "iWave"
diff --git a/src/mainboard/iwave/iWRainbowG6/Kconfig b/src/mainboard/iwave/iWRainbowG6/Kconfig
deleted file mode 100644
index c441063dfd..0000000000
--- a/src/mainboard/iwave/iWRainbowG6/Kconfig
+++ /dev/null
@@ -1,33 +0,0 @@
-if BOARD_IWAVE_RAINBOW_G6
-
-# TODO: move options to chipset components as appropriate
-config BOARD_SPECIFIC_OPTIONS # dummy
-	def_bool y
-	select CPU_INTEL_SOCKET_441
-	select SOC_INTEL_SCH
-	select HAVE_PIRQ_TABLE
-#	select HAVE_MP_TABLE
-	select UDELAY_LAPIC
-	select HAVE_ACPI_TABLES
-	select BOARD_ROMSIZE_KB_1024
-
-config MAINBOARD_DIR
-	string
-	default iwave/iWRainbowG6
-
-config MAINBOARD_PART_NUMBER
-	string
-	default "iWRainbowG6"
-
-config MMCONF_BASE_ADDRESS
-	hex
-	default 0xe0000000
-
-config IRQ_SLOT_COUNT
-	int
-	default 10
-
-# This mainboard might have a higher clocked UART or might not be able to run
-# serial output at 115200 baud
-
-endif
diff --git a/src/mainboard/iwave/iWRainbowG6/Kconfig.name b/src/mainboard/iwave/iWRainbowG6/Kconfig.name
deleted file mode 100644
index d2be66239f..0000000000
--- a/src/mainboard/iwave/iWRainbowG6/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_IWAVE_RAINBOW_G6
-	bool "iWRainbowG6"
diff --git a/src/mainboard/iwave/iWRainbowG6/Makefile.inc b/src/mainboard/iwave/iWRainbowG6/Makefile.inc
deleted file mode 100644
index f9621db6b3..0000000000
--- a/src/mainboard/iwave/iWRainbowG6/Makefile.inc
+++ /dev/null
@@ -1 +0,0 @@
-ramstage-y += cstates.c
diff --git a/src/mainboard/iwave/iWRainbowG6/acpi/cpu.asl b/src/mainboard/iwave/iWRainbowG6/acpi/cpu.asl
deleted file mode 100644
index 7535b51ba4..0000000000
--- a/src/mainboard/iwave/iWRainbowG6/acpi/cpu.asl
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/* Intel Core (2) Duo CPU node support
- *
- * Note: The ACPI P_BLK on the ICH7 (and probably others) lives at
- * PMBASE + 0x10, and it's 0x06 bytes long. On ICH8 it's 8 bytes.
- *
- * The second CPU core does not need its own P_BLK.
- */
-
-Scope(\_PR)
-{
-	Processor(
-		CPU1,	// name of cpu/core 0
-		1,	// numeric id of cpu/core
-		0x510,	// ACPI P_BLK base address
-		6	// ACPI P_BLK size
-	)
-	{
-		// TODO: _PDT
-	}
-
-	Processor(
-		CPU2,	// name of cpu/core 1
-		2,	// numeric id of cpu/core 1
-		0,	// ACPI P_BLK base address
-		0)	// ACPI P_BLK size
-	{
-		// TODO: _PDT
-	}
-}	// End _PR
diff --git a/src/mainboard/iwave/iWRainbowG6/acpi/ec.asl b/src/mainboard/iwave/iWRainbowG6/acpi/ec.asl
deleted file mode 100644
index 63abc00ccc..0000000000
--- a/src/mainboard/iwave/iWRainbowG6/acpi/ec.asl
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-Device(EC0)
-{
-	Name (_HID, EISAID("PNP0C09"))
-	Name (_UID, 1)
-
-	// _REG method requires that an operation region be defined.
-	OperationRegion (ERAM, EmbeddedControl, 0x00, 0xff)
-	Field (ERAM, ByteAcc, Lock, Preserve)
-	{
-	}
-
-	Method (_CRS, 0, Serialized)
-	{
-		Name (ECMD, ResourceTemplate()
-		{
-			IO (Decode16, 0x62, 0x62, 0, 1)
-			IO (Decode16, 0x66, 0x66, 0, 1)
-		})
-
-		Return (ECMD)
-	}
-
-	Method (_REG, 2)
-	{
-		// This method is needed by Windows XP/2000
-		// for EC initialization before a driver
-		// is loaded
-	}
-
-	Name (_GPE, 23)	// GPI07 / GPE23 -> Runtime SCI
-
-	// TODO EC Query methods
-
-	// TODO Scope _SB devices for AC power, LID, Power button
-
-}
diff --git a/src/mainboard/iwave/iWRainbowG6/acpi/northbridge_pci_irqs.asl b/src/mainboard/iwave/iWRainbowG6/acpi/northbridge_pci_irqs.asl
deleted file mode 100644
index efb94c6745..0000000000
--- a/src/mainboard/iwave/iWRainbowG6/acpi/northbridge_pci_irqs.asl
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/* This is board specific information: IRQ routing for the
- * i945
- */
-
-
-// PCI Interrupt Routing
-Method(_PRT)
-{
-	If (PICM) {
-		Return (Package() {
-			// PCIe Graphics		0:1.0
-			Package() { 0x0001ffff, 0, 0, 16 },
-			Package() { 0x0001ffff, 1, 0, 17 },
-			Package() { 0x0001ffff, 2, 0, 18 },
-			Package() { 0x0001ffff, 3, 0, 19 },
-			// Onboard graphics (IGD)	0:2.0
-			Package() { 0x0002ffff, 0, 0, 16 },
-			// High Definition Audio	0:1b.0
-			Package() { 0x001bffff, 0, 0, 16 },
-			// PCIe Root Ports		0:1c.x
-			Package() { 0x001cffff, 0, 0, 16 },
-			Package() { 0x001cffff, 1, 0, 17 },
-			Package() { 0x001cffff, 2, 0, 18 },
-			Package() { 0x001cffff, 3, 0, 19 },
-			// USB and EHCI			0:1d.x
-			Package() { 0x001dffff, 0, 0, 23 },
-			Package() { 0x001dffff, 1, 0, 19 },
-			Package() { 0x001dffff, 2, 0, 18 },
-			Package() { 0x001dffff, 3, 0, 16 },
-			// AC97/IDE				0:1e.2, 0:1e.3
-			Package() { 0x001effff, 0, 0, 17 },
-			Package() { 0x001effff, 1, 0, 20 },
-			// LPC device			0:1f.0
-			Package() { 0x001fffff, 0, 0, 18 },
-			Package() { 0x001fffff, 1, 0, 19},
-		})
-	} Else {
-		Return (Package() {
-			// PCIe Graphics		0:1.0
-			Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
-			Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
-			Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
-			Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
-			// Onboard graphics (IGD)	0:2.0
-			Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
-			// High Definition Audio	0:1b.0
-			Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
-			// PCIe Root Ports		0:1c.x
-			Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
-			Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
-			Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
-			Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
-			// USB and EHCI			0:1d.x
-			Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 },
-			Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
-			Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
-			Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKA, 0 },
-			// AC97/IDE			0:1e.2, 0:1e.3
-			Package() { 0x001effff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
-			Package() { 0x001effff, 1, \_SB.PCI0.LPCB.LNKE, 0 },
-			// LPC device			0:1f.0
-			Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKC, 0 },
-			Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
-		})
-	}
-}
diff --git a/src/mainboard/iwave/iWRainbowG6/acpi/platform.asl b/src/mainboard/iwave/iWRainbowG6/acpi/platform.asl
deleted file mode 100644
index 8e6d794a9a..0000000000
--- a/src/mainboard/iwave/iWRainbowG6/acpi/platform.asl
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/* The APM port can be used for generating software SMIs */
-
-OperationRegion (APMP, SystemIO, 0xb2, 2)
-Field (APMP, ByteAcc, NoLock, Preserve)
-{
-	APMC, 8,	// APM command
-	APMS, 8		// APM status
-}
-
-/* Port 80 POST */
-
-OperationRegion (POST, SystemIO, 0x80, 1)
-Field (POST, ByteAcc, Lock, Preserve)
-{
-	DBG0, 8
-}
-
-/* SMI I/O Trap */
-Method(TRAP, 1, Serialized)
-{
-	Store (Arg0, SMIF)	// SMI Function
-	//Store (0, TRP0)		// Generate trap
-	Return (SMIF)		// Return value of SMI handler
-}
-
-/* The _PIC method is called by the OS to choose between interrupt
- * routing via the i8259 interrupt controller or the APIC.
- *
- * _PIC is called with a parameter of 0 for i8259 configuration and
- * with a parameter of 1 for Local Apic/IOAPIC configuration.
- */
-
-Method(_PIC, 1)
-{
-	// Remember the OS' IRQ routing choice.
-	Store(Arg0, PICM)
-}
-
-/* The _PTS method (Prepare To Sleep) is called before the OS is
- * entering a sleep state. The sleep state number is passed in Arg0
- */
-
-Method(_PTS,1)
-{
-	// Call a trap so SMI can prepare for Sleep as well.
-	// TRAP(0x55)
-}
-
-/* The _WAK method is called on system wakeup */
-
-Method(_WAK,1)
-{
-	// CPU specific part
-
-	// Notify PCI Express slots in case a card
-	// was inserted while a sleep state was active.
-
-	// Are we going to S3?
-	If (LEqual(Arg0, 3)) {
-		// ..
-	}
-
-	// Are we going to S4?
-	If (LEqual(Arg0, 4)) {
-		// ..
-	}
-
-	// TODO: Windows XP SP2 P-State restore
-
-	Return(Package(){0,0})
-}
diff --git a/src/mainboard/iwave/iWRainbowG6/acpi/sleepstates.asl b/src/mainboard/iwave/iWRainbowG6/acpi/sleepstates.asl
deleted file mode 100644
index c05835ac3c..0000000000
--- a/src/mainboard/iwave/iWRainbowG6/acpi/sleepstates.asl
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-Name(\_S0, Package(4){0x0,0x0,0,0})
-Name(\_S1, Package(4){0x1,0x0,0,0})
-Name(\_S3, Package(4){0x5,0x0,0,0})
-Name(\_S4, Package(4){0x6,0x0,0,0})
-Name(\_S5, Package(4){0x7,0x0,0,0})
diff --git a/src/mainboard/iwave/iWRainbowG6/acpi/southbridge_pci_irqs.asl b/src/mainboard/iwave/iWRainbowG6/acpi/southbridge_pci_irqs.asl
deleted file mode 100644
index 67915f281f..0000000000
--- a/src/mainboard/iwave/iWRainbowG6/acpi/southbridge_pci_irqs.asl
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/* This is board specific information: IRQ routing for the
- * 0:1e.0 PCI bridge of the ICH7
- */
-
-If (PICM) {
-	Return (Package() {
-		Package() { 0x0000ffff, 0, 0, 16},
-
-		Package() { 0x0001ffff, 0, 0, 20},
-		Package() { 0x0001ffff, 1, 0, 21},
-		Package() { 0x0001ffff, 2, 0, 22},
-		Package() { 0x0001ffff, 3, 0, 23},
-
-		Package() { 0x0002ffff, 0, 0, 21},
-		Package() { 0x0002ffff, 1, 0, 22},
-		Package() { 0x0002ffff, 2, 0, 23},
-		Package() { 0x0002ffff, 3, 0, 20},
-
-		Package() { 0x0003ffff, 0, 0, 22},
-		Package() { 0x0003ffff, 1, 0, 23},
-		Package() { 0x0003ffff, 2, 0, 20},
-		Package() { 0x0003ffff, 3, 0, 21},
-
-		Package() { 0x0004ffff, 0, 0, 23},
-		Package() { 0x0004ffff, 1, 0, 20},
-		Package() { 0x0004ffff, 2, 0, 21},
-		Package() { 0x0004ffff, 3, 0, 22},
-
-		Package() { 0x0005ffff, 0, 0, 19},
-		Package() { 0x0005ffff, 1, 0, 18},
-		Package() { 0x0005ffff, 2, 0, 17},
-		Package() { 0x0005ffff, 3, 0, 16},
-
-		Package() { 0x0006ffff, 0, 0, 18},
-		Package() { 0x0006ffff, 1, 0, 17},
-		Package() { 0x0006ffff, 2, 0, 16},
-		Package() { 0x0006ffff, 3, 0, 19},
-
-		Package() { 0x0009ffff, 0, 0, 21},
-		Package() { 0x0009ffff, 1, 0, 22},
-		Package() { 0x0009ffff, 2, 0, 23},
-		Package() { 0x0009ffff, 3, 0, 20},
-	})
-} Else {
-	Return (Package() {
-		Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0},
-
-		Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKE, 0},
-		Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKF, 0},
-		Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKG, 0},
-		Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKH, 0},
-
-		Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKF, 0},
-		Package() { 0x0002ffff, 1, \_SB.PCI0.LPCB.LNKG, 0},
-		Package() { 0x0002ffff, 2, \_SB.PCI0.LPCB.LNKH, 0},
-		Package() { 0x0002ffff, 3, \_SB.PCI0.LPCB.LNKE, 0},
-
-		Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKG, 0},
-		Package() { 0x0003ffff, 1, \_SB.PCI0.LPCB.LNKH, 0},
-		Package() { 0x0003ffff, 2, \_SB.PCI0.LPCB.LNKE, 0},
-		Package() { 0x0003ffff, 3, \_SB.PCI0.LPCB.LNKF, 0},
-
-		Package() { 0x0004ffff, 0, \_SB.PCI0.LPCB.LNKH, 0},
-		Package() { 0x0004ffff, 1, \_SB.PCI0.LPCB.LNKE, 0},
-		Package() { 0x0004ffff, 2, \_SB.PCI0.LPCB.LNKF, 0},
-		Package() { 0x0004ffff, 3, \_SB.PCI0.LPCB.LNKG, 0},
-
-		Package() { 0x0005ffff, 0, \_SB.PCI0.LPCB.LNKD, 0},
-		Package() { 0x0005ffff, 1, \_SB.PCI0.LPCB.LNKC, 0},
-		Package() { 0x0005ffff, 2, \_SB.PCI0.LPCB.LNKB, 0},
-		Package() { 0x0005ffff, 3, \_SB.PCI0.LPCB.LNKA, 0},
-
-		Package() { 0x0006ffff, 0, \_SB.PCI0.LPCB.LNKC, 0},
-		Package() { 0x0006ffff, 1, \_SB.PCI0.LPCB.LNKB, 0},
-		Package() { 0x0006ffff, 2, \_SB.PCI0.LPCB.LNKA, 0},
-		Package() { 0x0006ffff, 3, \_SB.PCI0.LPCB.LNKD, 0},
-
-		Package() { 0x0009ffff, 0, \_SB.PCI0.LPCB.LNKF, 0},
-		Package() { 0x0009ffff, 1, \_SB.PCI0.LPCB.LNKG, 0},
-		Package() { 0x0009ffff, 2, \_SB.PCI0.LPCB.LNKH, 0},
-		Package() { 0x0009ffff, 3, \_SB.PCI0.LPCB.LNKE, 0},
-	})
-}
diff --git a/src/mainboard/iwave/iWRainbowG6/acpi/superio.asl b/src/mainboard/iwave/iWRainbowG6/acpi/superio.asl
deleted file mode 100644
index 38343a587a..0000000000
--- a/src/mainboard/iwave/iWRainbowG6/acpi/superio.asl
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-
-Device (SIO1)
-{
-	Name (_HID, EISAID("PNP0A05"))
-	Name (_UID, 1)
-
-	Device (UAR1)
-	{
-		Name(_HID, EISAID("PNP0501"))
-		Name(_UID, 1)
-
-		// Some methods need an implementation here:
-		// missing: _STA, _DIS, _CRS, _PRS,
-		// missing: _SRS, _PS0, _PS3
-	}
-
-	Device (UAR2)
-	{
-		Name(_HID, EISAID("PNP0501"))
-		Name(_UID, 2)
-
-		// Some methods need an implementation here:
-		// missing: _STA, _DIS, _CRS, _PRS,
-		// missing: _SRS, _PS0, _PS3
-	}
-}
diff --git a/src/mainboard/iwave/iWRainbowG6/acpi/thermal.asl b/src/mainboard/iwave/iWRainbowG6/acpi/thermal.asl
deleted file mode 100644
index de8fcddeab..0000000000
--- a/src/mainboard/iwave/iWRainbowG6/acpi/thermal.asl
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-// Thermal Zone
-
-Scope (\_TZ)
-{
-	ThermalZone (THRM)
-	{
-
-		// FIXME these could/should be read from the
-		// GNVS area, so they can be controlled by
-		// coreboot
-		Name(TC1V, 0x04)
-		Name(TC2V, 0x03)
-		Name(TSPV, 0x64)
-
-		// At which temperature should the OS start
-		// active cooling?
-		Method (_AC0, 0, Serialized)
-		{
-			Return (0xf5c) // Value for Rocky
-		}
-
-		// Method (_AC1, 0, Serialized)
-		// {
-		// 	Return (0xf5c)
-		// }
-
-		// Critical shutdown temperature
-		Method (_CRT, 0, Serialized)
-		{
-			Return (Add (0x0aac, 0x50)) // FIXME
-		}
-
-		// CPU throttling start temperature
-		Method (_PSV, 0, Serialized)
-		{
-			Return (0xaaf) // FIXME
-		}
-
-		// Get DTS Temperature
-		Method (_TMP, 0, Serialized)
-		{
-			Return (0xaac) // FIXME
-		}
-
-		// Processors used for active cooling
-		Method (_PSL, 0, Serialized)
-		{
-			If (MPEN) {
-				Return (Package() {\_PR.CP01, \_PR.CP02})
-			}
-			Return (Package() {\_PR.CP01})
-		}
-
-		// TC1 value for passive cooling
-		Method (_TC1, 0, Serialized)
-		{
-			Return (TC1V)
-		}
-
-		// TC2 value for passive cooling
-		Method (_TC2, 0, Serialized)
-		{
-			Return (TC2V)
-		}
-
-		// Sampling period for passive cooling
-		Method (_TSP, 0, Serialized)
-		{
-			Return (TSPV)
-		}
-
-
-	}
-}
diff --git a/src/mainboard/iwave/iWRainbowG6/acpi_tables.c b/src/mainboard/iwave/iWRainbowG6/acpi_tables.c
deleted file mode 100644
index 45b9da2e2c..0000000000
--- a/src/mainboard/iwave/iWRainbowG6/acpi_tables.c
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <types.h>
-#include <string.h>
-#include <console/console.h>
-#include <arch/acpi.h>
-#include <arch/ioapic.h>
-#include <arch/acpigen.h>
-#include <arch/smp/mpspec.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-
-#include "soc/intel/sch/nvs.h"
-
-void acpi_create_gnvs(global_nvs_t * gnvs)
-{
-	memset((void *)gnvs, 0, sizeof(*gnvs));
-	gnvs->apic = 1;
-	gnvs->mpen = 1;		/* Enable Multi Processing. */
-
-	/* Enable both COM ports. */
-	gnvs->cmap = 0x01;
-	gnvs->cmbp = 0x01;
-}
-
-unsigned long acpi_fill_madt(unsigned long current)
-{
-	/* Local APICs */
-	current = acpi_create_madt_lapics(current);
-
-	/* IOAPIC */
-	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
-					   2, IO_APIC_ADDR, 0);
-
-	/* INT_SRC_OVR */
-	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
-						current, 0, 0, 2, 0);
-	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
-						current, 0, 9, 9,
-						MP_IRQ_TRIGGER_LEVEL |
-						MP_IRQ_POLARITY_HIGH);
-
-	return current;
-}
diff --git a/src/mainboard/iwave/iWRainbowG6/board_info.txt b/src/mainboard/iwave/iWRainbowG6/board_info.txt
deleted file mode 100644
index ad25a93caa..0000000000
--- a/src/mainboard/iwave/iWRainbowG6/board_info.txt
+++ /dev/null
@@ -1,3 +0,0 @@
-Board name: iW-RainboW-G6
-Category: half
-Board URL: http://www.iwavesystems.com/iW-RainbowG6.htm
diff --git a/src/mainboard/iwave/iWRainbowG6/cmos.layout b/src/mainboard/iwave/iWRainbowG6/cmos.layout
deleted file mode 100644
index 1081a15049..0000000000
--- a/src/mainboard/iwave/iWRainbowG6/cmos.layout
+++ /dev/null
@@ -1,111 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# Copyright (C) 2007-2009 coresystems GmbH
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; version 2 of
-# the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-
-# -----------------------------------------------------------------
-entries
-
-# -----------------------------------------------------------------
-# Status Register A
-# -----------------------------------------------------------------
-# Status Register B
-# -----------------------------------------------------------------
-# Status Register C
-#96           4       r       0        status_c_rsvd
-#100          1       r       0        uf_flag
-#101          1       r       0        af_flag
-#102          1       r       0        pf_flag
-#103          1       r       0        irqf_flag
-# -----------------------------------------------------------------
-# Status Register D
-#104          7       r       0        status_d_rsvd
-#111          1       r       0        valid_cmos_ram
-# -----------------------------------------------------------------
-# Diagnostic Status Register
-#112          8       r       0        diag_rsvd1
-
-# -----------------------------------------------------------------
-0          120       r       0        reserved_memory
-#120        264       r       0        unused
-
-# -----------------------------------------------------------------
-# RTC_BOOT_BYTE (coreboot hardcoded)
-384          1       e       4        boot_option
-388          4       h       0        reboot_counter
-#390          2       r       0        unused?
-
-# -----------------------------------------------------------------
-# coreboot config options: console
-#392          3       r       0        unused
-395          4       e       6        debug_level
-#399          1       r       0        unused
-
-# coreboot config options: cpu
-400          1       e       2        hyper_threading
-#401          7       r       0        unused
-
-# coreboot config options: southbridge
-408          1       e       1        nmi
-409          2       e       7        power_on_after_fail
-#411          5       r       0        unused
-
-# coreboot config options: bootloader
-416        512       s       0        boot_devices
-#928         40       r       0        unused
-
-968          1       e       2        ethernet1
-969          1       e       2        ethernet2
-970          1       e       2        ethernet3
-
-#971          13       r       0        unused
-
-# coreboot config options: check sums
-984         16       h       0        check_sum
-#1000        24       r       0        amd_reserved
-
-# RAM initialization internal data
-1024         8       r       0        C0WL0REOST
-1032         8       r       0        C1WL0REOST
-1040         8       r       0        RCVENMT
-1048         4       r       0        C0DRT1
-1052         4       r       0        C1DRT1
-
-# -----------------------------------------------------------------
-
-enumerations
-
-#ID value   text
-1     0     Disable
-1     1     Enable
-2     0     Enable
-2     1     Disable
-4     0     Fallback
-4     1     Normal
-6     1     Emergency
-6     2     Alert
-6     3     Critical
-6     4     Error
-6     5     Warning
-6     6     Notice
-6     7     Info
-6     8     Debug
-6     9     Spew
-7     0     Disable
-7     1     Enable
-7     2     Keep
-# -----------------------------------------------------------------
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/iwave/iWRainbowG6/cstates.c b/src/mainboard/iwave/iWRainbowG6/cstates.c
deleted file mode 100644
index 2d543ff62e..0000000000
--- a/src/mainboard/iwave/iWRainbowG6/cstates.c
+++ /dev/null
@@ -1,7 +0,0 @@
-#include <device/device.h>
-#include <arch/x86/include/arch/acpigen.h>
-
-int get_cst_entries(acpi_cstate_t **entries)
-{
-	return 0;
-}
diff --git a/src/mainboard/iwave/iWRainbowG6/devicetree.cb b/src/mainboard/iwave/iWRainbowG6/devicetree.cb
deleted file mode 100644
index b13d87300b..0000000000
--- a/src/mainboard/iwave/iWRainbowG6/devicetree.cb
+++ /dev/null
@@ -1,40 +0,0 @@
-chip soc/intel/sch
-	# IGD Displays
-	register "gfx.ndid" = "3"
-	register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
-
-	# PIRQ routing
-	register "pirqa_routing" = "0xa"
-	register "pirqb_routing" = "0xb"
-	register "pirqc_routing" = "0x5"
-	register "pirqd_routing" = "0xf"
-	register "pirqe_routing" = "0x80"
-	register "pirqf_routing" = "0x80"
-	register "pirqg_routing" = "0x80"
-	register "pirqh_routing" = "0x80"
-
-	device cpu_cluster 0 on
-		chip cpu/intel/socket_441
-			device lapic 0 on end
-		end
-	end
-
-	device domain 0 on
-		device pci 00.0 on end # host bridge
-		device pci 02.0 on end # Integrated Graphics and Video Device
-
-		device pci 1a.0 on end  # 26 0 USB Client
-		device pci 1b.0 on end  # 27 0 HD Audio Controller
-		device pci 1c.0 on end  # 28 0 PCI Express Port 1
-		device pci 1c.1 on end  # 28 1 PCI Express Port 2
-		device pci 1d.0 on end  # USB Classic UHCI Controller 1
-		device pci 1d.1 on end  # USB Classic UHCI Controller 2
-		device pci 1d.2 on end  # USB Classic UHCI Controller 3
-		device pci 1d.7 on end  # USB2 EHCI Controller
-		device pci 1e.0 on end  # SDIO/MMC Port 0
-		device pci 1e.1 on end  # SDIO/MMC Port 1
-		device pci 1e.2 on end  # SDIO/MMC Port 2
-		device pci 1f.0 on end  # LPC bridge
-		device pci 1f.1 on end  # PATA Controller
-	end
-end
diff --git a/src/mainboard/iwave/iWRainbowG6/dsdt.asl b/src/mainboard/iwave/iWRainbowG6/dsdt.asl
deleted file mode 100644
index 0dc46f2caa..0000000000
--- a/src/mainboard/iwave/iWRainbowG6/dsdt.asl
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-DefinitionBlock(
-	"dsdt.aml",
-	"DSDT",
-	0x02,		// DSDT revision: ACPI v2.0
-	"COREv4",	// OEM id
-	"COREBOOT",	// OEM table id
-	0x20090419	// OEM revision
-)
-{
-	// Some generic macros
-	#include "acpi/platform.asl"
-
-	// global NVS and variables
-	#include <soc/intel/sch/acpi/globalnvs.asl>
-
-	// General Purpose Events
-	//#include "acpi/gpe.asl"
-
-	//#include "acpi/thermal.asl"
-
-	Scope (\_SB) {
-		Device (PCI0)
-		{
-			#include <soc/intel/sch/acpi/sch.asl>
-		}
-	}
-
-	/* Chipset specific sleep states */
-	#include <soc/intel/sch/acpi/sleepstates.asl>
-}
diff --git a/src/mainboard/iwave/iWRainbowG6/fadt.c b/src/mainboard/iwave/iWRainbowG6/fadt.c
deleted file mode 100644
index 86aa6063ed..0000000000
--- a/src/mainboard/iwave/iWRainbowG6/fadt.c
+++ /dev/null
@@ -1,151 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <string.h>
-#include <device/pci.h>
-#include <arch/acpi.h>
-#include <cpu/x86/smm.h>
-
-void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
-{
-	acpi_header_t *header = &(fadt->header);
-	u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f, 0)),
-				       0x40) & 0xfffe;
-
-	memset((void *)fadt, 0, sizeof(acpi_fadt_t));
-	memcpy(header->signature, "FACP", 4);
-	header->length = sizeof(acpi_fadt_t);
-	header->revision = 3;
-	memcpy(header->oem_id, OEM_ID, 6);
-	memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
-	memcpy(header->asl_compiler_id, ASLC, 4);
-	header->asl_compiler_revision = 1;
-
-	fadt->firmware_ctrl = (unsigned long)facs;
-	fadt->dsdt = (unsigned long)dsdt;
-	fadt->model = 1;
-	fadt->preferred_pm_profile = PM_MOBILE;
-
-	fadt->sci_int = 0x9;
-	fadt->smi_cmd = APM_CNT;
-	fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
-	fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
-	fadt->s4bios_req = 0x0;
-	fadt->pstate_cnt = APM_CNT_PST_CONTROL;
-
-	fadt->pm1a_evt_blk = pmbase;
-	fadt->pm1b_evt_blk = 0x0;
-	fadt->pm1a_cnt_blk = pmbase + 0x4;
-	fadt->pm1b_cnt_blk = 0x0;
-	fadt->pm2_cnt_blk = pmbase + 0x20;
-	fadt->pm_tmr_blk = pmbase + 0x8;
-	fadt->gpe0_blk = pmbase + 0x28;
-	fadt->gpe1_blk = 0;
-
-	fadt->pm1_evt_len = 4;
-	fadt->pm1_cnt_len = 2;
-	// XXX: pm2_cnt_len is probably wrong. find out right value (hint: it's != 0)
-	fadt->pm2_cnt_len = 2;
-	fadt->pm_tmr_len = 4;
-	fadt->gpe0_blk_len = 8;
-	fadt->gpe1_blk_len = 0;
-	fadt->gpe1_base = 0;
-	fadt->cst_cnt = APM_CNT_CST_CONTROL;
-	fadt->p_lvl2_lat = 1;
-	fadt->p_lvl3_lat = 85;
-	fadt->flush_size = 1024;
-	fadt->flush_stride = 16;
-	fadt->duty_offset = 1;
-	fadt->duty_width = 0;
-	fadt->day_alrm = 0xd;
-	fadt->mon_alrm = 0x00;
-	fadt->century = 0x00;
-	fadt->iapc_boot_arch = 0x03;
-
-	fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
-	    ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
-	    ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK;
-
-	fadt->reset_reg.space_id = 0;
-	fadt->reset_reg.bit_width = 0;
-	fadt->reset_reg.bit_offset = 0;
-	fadt->reset_reg.resv = 0;
-	fadt->reset_reg.addrl = 0x0;
-	fadt->reset_reg.addrh = 0x0;
-
-	fadt->reset_value = 0;
-	fadt->x_firmware_ctl_l = (unsigned long)facs;
-	fadt->x_firmware_ctl_h = 0;
-	fadt->x_dsdt_l = (unsigned long)dsdt;
-	fadt->x_dsdt_h = 0;
-
-	fadt->x_pm1a_evt_blk.space_id = 1;
-	fadt->x_pm1a_evt_blk.bit_width = 32;
-	fadt->x_pm1a_evt_blk.bit_offset = 0;
-	fadt->x_pm1a_evt_blk.resv = 0;
-	fadt->x_pm1a_evt_blk.addrl = pmbase;
-	fadt->x_pm1a_evt_blk.addrh = 0x0;
-
-	fadt->x_pm1b_evt_blk.space_id = 1;
-	fadt->x_pm1b_evt_blk.bit_width = 0;
-	fadt->x_pm1b_evt_blk.bit_offset = 0;
-	fadt->x_pm1b_evt_blk.resv = 0;
-	fadt->x_pm1b_evt_blk.addrl = 0x0;
-	fadt->x_pm1b_evt_blk.addrh = 0x0;
-
-	fadt->x_pm1a_cnt_blk.space_id = 1;
-	fadt->x_pm1a_cnt_blk.bit_width = 16;
-	fadt->x_pm1a_cnt_blk.bit_offset = 0;
-	fadt->x_pm1a_cnt_blk.resv = 0;
-	fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
-	fadt->x_pm1a_cnt_blk.addrh = 0x0;
-
-	fadt->x_pm1b_cnt_blk.space_id = 1;
-	fadt->x_pm1b_cnt_blk.bit_width = 0;
-	fadt->x_pm1b_cnt_blk.bit_offset = 0;
-	fadt->x_pm1b_cnt_blk.resv = 0;
-	fadt->x_pm1b_cnt_blk.addrl = 0x0;
-	fadt->x_pm1b_cnt_blk.addrh = 0x0;
-
-	fadt->x_pm2_cnt_blk.space_id = 1;
-	fadt->x_pm2_cnt_blk.bit_width = 8;
-	fadt->x_pm2_cnt_blk.bit_offset = 0;
-	fadt->x_pm2_cnt_blk.resv = 0;
-	fadt->x_pm2_cnt_blk.addrl = pmbase + 0x20;
-	fadt->x_pm2_cnt_blk.addrh = 0x0;
-
-	fadt->x_pm_tmr_blk.space_id = 1;
-	fadt->x_pm_tmr_blk.bit_width = 32;
-	fadt->x_pm_tmr_blk.bit_offset = 0;
-	fadt->x_pm_tmr_blk.resv = 0;
-	fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
-	fadt->x_pm_tmr_blk.addrh = 0x0;
-
-	fadt->x_gpe0_blk.space_id = 1;
-	fadt->x_gpe0_blk.bit_width = 64;
-	fadt->x_gpe0_blk.bit_offset = 0;
-	fadt->x_gpe0_blk.resv = 0;
-	fadt->x_gpe0_blk.addrl = pmbase + 0x28;
-	fadt->x_gpe0_blk.addrh = 0x0;
-
-	fadt->x_gpe1_blk.space_id = 1;
-	fadt->x_gpe1_blk.bit_width = 0;
-	fadt->x_gpe1_blk.bit_offset = 0;
-	fadt->x_gpe1_blk.resv = 0;
-	fadt->x_gpe1_blk.addrl = 0x0;
-	fadt->x_gpe1_blk.addrh = 0x0;
-
-	header->checksum = acpi_checksum((void *)fadt, header->length);
-}
diff --git a/src/mainboard/iwave/iWRainbowG6/hda_verb.c b/src/mainboard/iwave/iWRainbowG6/hda_verb.c
deleted file mode 100644
index 5e6f5950e3..0000000000
--- a/src/mainboard/iwave/iWRainbowG6/hda_verb.c
+++ /dev/null
@@ -1,93 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2009-2010 iWave Systems
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <device/azalia_device.h>
-
-const u32 cim_verb_data[] = {
-	/* coreboot specific header */
-	0x111d76d5,		// Codec Vendor / Device ID: IDT 92HD81
-	0x00000000,		// Subsystem ID
-	0x0000000a,		// Number of jacks
-
-	/* NID 0x0a, Port A (capless headphone) */
-	0x0A71C40,
-	0x0A71D10,
-	0x0A71EA1,
-	0x0A71F02,
-
-	/* NID 0x0b, Port B (capless headphone) */
-	0x0B71C1F,
-	0x0B71D10,
-	0x0B71E21,
-	0x0B71F02,
-
-	/*
-	 * NID 0x0c, Port C (Line IN/OUT+MIC for YD/UA revisions, and
-	 * Line IN+MIC for TA revision)
-	 */
-	0x0C71CF0,
-	0x0C71D00,
-	0x0C71E00,
-	0x0C71F40,
-
-	/* NID 0x0d, Port D (BTL output - EAPD control) */
-	0x0D71C10,
-	0x0D71D41,
-	0x0D71E10,
-	0x0D71F10,
-
-	/* NID 0x0e, Port E (Line IN/OUT) */
-	0x0E71CF0,
-	0x0E71D00,
-	0x0E71E00,
-	0x0E71F40,
-
-	/* NID 0x0f, Port F (Line IN/OUT, MIC) */
-	0x0F71CF0,
-	0x0F71D00,
-	0x0F71E00,
-	0x0F71F40,
-
-	/* NID 0x10, MonoOut (output-only) */
-	0x1071CF0,
-	0x1071D00,
-	0x1071EF0,
-	0x1071F40,
-
-	/* NID 0x10, DigMic0 (Digital Microphone 0) */
-	0x1171CF0,
-	0x1171D00,
-	0x1171E00,
-	0x1171F40,
-
-	/* NID 0x1f, Dig0Pin (First Digital Output Pin) */
-	0x1F71C50,
-	0x1F71D21,
-	0x1F71E40,
-	0x1F71F10,
-
-	/* NID 0x20, Dig1Pin (Second Digital Output Pin / DMIC Input Pin) */
-	0x2071CF0,
-	0x2071D00,
-	0x2071E00,
-	0x2071F40,
-
-	/* BTL Gain */
-	0x017F417, /* Gain = 16.79dB */
-};
-
-const u32 pc_beep_verbs[0] = {};
-
-AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/iwave/iWRainbowG6/irq_tables.c b/src/mainboard/iwave/iWRainbowG6/irq_tables.c
deleted file mode 100644
index 8ad7e25e4a..0000000000
--- a/src/mainboard/iwave/iWRainbowG6/irq_tables.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2008 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/pirq_routing.h>
-
-static const struct irq_routing_table intel_irq_routing_table = {
-	PIRQ_SIGNATURE,         /* u32 signature */
-	PIRQ_VERSION,           /* u16 version */
-	32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* Max. number of devices on the bus */
-	0x00,                   /* Interrupt router bus */
-	(0x1f << 3) | 0x0,      /* Interrupt router dev */
-	0,                      /* IRQs devoted exclusively to PCI usage */
-	0x8086,                 /* Vendor */
-	0x8119,                 /* Device*/
-	0,                      /* Miniport */
-	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
-	0xdf,                   /* Checksum (has to be set to some value that
-	                         * would give 0 after the sum of all bytes
-	                         * for this structure (including checksum).
-	                         */
-	{
-		/* bus,        dev | fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
-		{0x00, (0x02 << 3) | 0x0, {{0x60, 0x5cb8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
-		{0x00, (0x1e << 3) | 0x0, {{0x60, 0x5cb8}, {0x61, 0x5cb8}, {0x62, 0x5cb8}, {0x00, 0x0000}}, 0x0, 0x0},
-		{0x00, (0x1f << 3) | 0x0, {{0x62, 0x5cb8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
-		{0x00, (0x1a << 3) | 0x0, {{0x60, 0x5cb8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
-		{0x00, (0x1d << 3) | 0x0, {{0x64, 0x8200}, {0x65, 0x8200}, {0x66, 0x8200}, {0x67, 0x8200}}, 0x0, 0x0},
-		{0x00, (0x1b << 3) | 0x0, {{0x60, 0x5cb8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
-		{0x00, (0x1c << 3) | 0x0, {{0x60, 0x5cb8}, {0x61, 0x5cb8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
-		{0x01, (0x00 << 3) | 0x0, {{0x60, 0x5cb8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
-		{0x02, (0x00 << 3) | 0x0, {{0x61, 0x5cb8}, {0x62, 0x5cb8}, {0x63, 0x5cb8}, {0x60, 0x5cb8}}, 0x2, 0x0},
-		{0x00, (0x00 << 3) | 0x0, {{0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
-	}
-};
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
-	return copy_pirq_routing_table(addr, &intel_irq_routing_table);
-}
diff --git a/src/mainboard/iwave/iWRainbowG6/mptable.c b/src/mainboard/iwave/iWRainbowG6/mptable.c
deleted file mode 100644
index 5ba63bc0cd..0000000000
--- a/src/mainboard/iwave/iWRainbowG6/mptable.c
+++ /dev/null
@@ -1,101 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2008 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <arch/smp/mpspec.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-
-void *smp_write_config_table(void *v)
-{
-	struct mp_config_table *mc;
-	int isa_bus;
-
-	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-	mptable_init(mc, LOCAL_APIC_ADDR);
-
-	smp_write_processors(mc);
-	mptable_write_buses(mc, NULL, &isa_bus);
-
-	smp_write_ioapic(mc, 2, 0x20, VIO_APIC_VADDR);
-	{
-		device_t dev;
-		struct resource *res;
-		dev = dev_find_slot(1, PCI_DEVFN(0x1e,0));
-		if (dev) {
-			res = find_resource(dev, PCI_BASE_ADDRESS_0);
-			if (res) {
-				smp_write_ioapic(mc, 3, 0x20, res->base);
-			}
-		}
-		dev = dev_find_slot(1, PCI_DEVFN(0x1c,0));
-		if (dev) {
-			res = find_resource(dev, PCI_BASE_ADDRESS_0);
-			if (res) {
-				smp_write_ioapic(mc, 4, 0x20, res->base);
-			}
-		}
-		dev = dev_find_slot(4, PCI_DEVFN(0x1e,0));
-		if (dev) {
-			res = find_resource(dev, PCI_BASE_ADDRESS_0);
-			if (res) {
-				smp_write_ioapic(mc, 5, 0x20, res->base);
-			}
-		}
-		dev = dev_find_slot(4, PCI_DEVFN(0x1c,0));
-		if (dev) {
-			res = find_resource(dev, PCI_BASE_ADDRESS_0);
-			if (res) {
-				smp_write_ioapic(mc, 8, 0x20, res->base);
-			}
-		}
-	}
-/*I/O Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#
-*/	smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_DEFAULT, 0x1, 0x0, 0x1, 0x0);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x1, 0x1, 0x1, 0x1);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x1, 0x0, 0x1, 0x2);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x1, 0x3, 0x1, 0x3);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x1, 0x4, 0x1, 0x4);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x1, 0x6, 0x1, 0x6);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x1, 0x7, 0x1, 0x7);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x1, 0x8, 0x1, 0x8);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x1, 0x9, 0x1, 0x9);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x1, 0xc, 0x1, 0xc);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x1, 0xd, 0x1, 0xd);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x1, 0xe, 0x1, 0xe);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x8, 0x1, 0x10);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x74, 0x1, 0x10);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x75, 0x1, 0x11);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x76, 0x1, 0x12);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x77, 0x1, 0x13);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x6c, 0x1, 0x10);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x78, 0x1, 0x10);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x79, 0x1, 0x11);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x7a, 0x1, 0x12);
-/*Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#*/
-	mptable_lintsrc(mc, isa_bus);
-	/* There is no extension information... */
-
-	/* Compute the checksums */
-	return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
-	void *v;
-	v = smp_write_floating_table(addr, 0);
-	return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/iwave/iWRainbowG6/romstage.c b/src/mainboard/iwave/iWRainbowG6/romstage.c
deleted file mode 100644
index a5c0c9ce12..0000000000
--- a/src/mainboard/iwave/iWRainbowG6/romstage.c
+++ /dev/null
@@ -1,379 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2009-2010 iWave Systems
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <string.h>
-#include <arch/io.h>
-#include <device/pci_def.h>
-#include <device/pnp_def.h>
-#include <cpu/x86/lapic.h>
-#include <cpu/x86/cache.h>
-#include <cpu/intel/romstage.h>
-#include <arch/cpu.h>
-#include <console/console.h>
-#if 0
-#include "ram/ramtest.c"
-#include "soc/intel/sch/early_smbus.c"
-#endif
-
-#define RFID_TEST 0
-
-#if RFID_TEST
-#define RFID_ADDR 0xA0
-#define RFID_SELECT_CARD_COMMAND 0x01
-#define SELECT_COMMAND_LENGTH 0x01
-
-#define SMBUS_BASE_ADDRESS 0x400
-
-static u32 sch_SMbase_read(void)
-{
-	u32 SMBusBase;
-
-	/* SMBus address */
-	SMBusBase = pci_read_config32(PCI_DEV(0, 0x1f, 0), 0x40);
-	SMBusBase &= 0xFFFF;
-	printk(BIOS_DEBUG, "SMBus base = %x\r\n", SMBusBase);
-	return SMBusBase;
-}
-
-static void sch_SMbase_init(void)
-{
-	u32 SMBusBase;
-
-	SMBusBase = sch_SMbase_read();
-	outb(0x3F, SMBusBase + SMBCLKDIV);
-}
-
-static void sch_SMbus_regs(void)
-{
-	u32 SMBusBase;
-
-	SMBusBase = sch_SMbase_read();
-	printk(BIOS_DEBUG, "SMBHSTCNT. =%x\r\n", inb(SMBusBase + SMBHSTCNT));
-	printk(BIOS_DEBUG, "SMBHSTSTS. =%x\r\n", inb(SMBusBase + SMBHSTSTS));
-	printk(BIOS_DEBUG, "SMBCLKDIV. =%x\r\n", inb(SMBusBase + SMBCLKDIV));
-
-	printk(BIOS_DEBUG, "SMBHSTADD. =%x\r\n", inb(SMBusBase + SMBHSTADD));
-	printk(BIOS_DEBUG, "SMBHSTCMD. =%x\r\n", inb(SMBusBase + SMBHSTCMD));
-}
-
-void smb_clear(void)
-{
-	u32 SMBusBase;
-
-	SMBusBase = sch_SMbase_read();
-	outb(0x00, SMBusBase + SMBHSTCNT);
-	outb(0x07, SMBusBase + SMBHSTSTS);
-}
-
-void data_clear(void)
-{
-	u32 SMBusBase;
-
-	SMBusBase = sch_SMbase_read();
-	outb(0x00, SMBusBase + SMBHSTDAT0);
-	outb(0x00, SMBusBase + SMBHSTCMD);
-	outb(0x00, SMBusBase + SMBHSTDAT1);
-	outb(0x00, SMBusBase + SMBHSTDATB);
-	outb(0x00, SMBusBase + (SMBHSTDATB + 0x1));
-	outb(0x00, SMBusBase + (SMBHSTDATB + 0x2));
-	outb(0x00, SMBusBase + (SMBHSTDATB + 0x3));
-	outb(0x00, SMBusBase + (SMBHSTDATB + 0x4));
-	outb(0x00, SMBusBase + (SMBHSTDATB + 0x5));
-	outb(0x00, SMBusBase + (SMBHSTDATB + 0x6));
-}
-
-void transaction1(unsigned char dev_addr)
-{
-	int temp, a;
-	u32 SMBusBase;
-
-	SMBusBase = sch_SMbase_read();
-	printk(BIOS_DEBUG, "Transaction 1");
-	//clear the control and status registers
-	smb_clear();
-	//clear the data register
-	data_clear();
-	//program TSA register
-	outb(dev_addr, SMBusBase + SMBHSTADD);
-	//program command register
-	outb(0x04, SMBusBase + SMBHSTCMD);
-	//write data register
-	outb(0x04, SMBusBase + SMBHSTDAT0);
-	outb(0x04, SMBusBase + SMBHSTDATB);
-
-	outb(0x09, SMBusBase + (SMBHSTDATB + 0x1));
-	outb(0x11, SMBusBase + (SMBHSTDATB + 0x2));
-	outb(0x22, SMBusBase + (SMBHSTDATB + 0x3));
-
-	//set the control register
-	outb(0x15, SMBusBase + SMBHSTCNT);
-	//check the status register for busy state
-	//sch_SMbus_regs ();
-	temp = inb(SMBusBase + SMBHSTSTS);
-	//printk(BIOS_DEBUG, "SMBus Busy.. status =%x\r\n",temp);
-	//printk(BIOS_DEBUG, "SMBHSTSTS. =%x\r\n",inb(SMBusBase+SMBHSTSTS));
-	do {
-		temp = inb(SMBusBase + SMBHSTSTS);
-		printk(BIOS_DEBUG, "SMBus Busy.. status =%x\r\n", temp);
-		//sch_SMbus_regs ();
-		printk(BIOS_DEBUG, "SMBHSTSTS. =%x\r\n",
-		       inb(SMBusBase + SMBHSTSTS));
-		if (temp > 0)
-			break;
-	} while (1);
-
-	switch (temp) {
-	case 1:
-		printk(BIOS_DEBUG, "SMBus Success");
-		break;
-	default:
-		printk(BIOS_DEBUG, "SMBus error %d", temp);
-		break;
-
-	}
-	sch_SMbus_regs();
-	printk(BIOS_DEBUG, "Command in TRansaction 1=%x\r\n\n",
-	       inb(SMBusBase + SMBHSTCMD));
-}
-
-void transaction2(unsigned char dev_addr)
-{
-	int temp, a;
-	u32 SMBusBase;
-
-	SMBusBase = sch_SMbase_read();
-	printk(BIOS_DEBUG, "Transaction 2");
-	//clear the control and status registers
-	smb_clear();
-	//clear the data register
-	data_clear();
-	//program TSA register
-	outb(dev_addr, SMBusBase + SMBHSTADD);
-	//program command register
-	outb(0x03, SMBusBase + SMBHSTCMD);
-	//write data register
-	outb(0x02, SMBusBase + SMBHSTDAT0);
-	outb(0x03, SMBusBase + SMBHSTDATB);
-	outb(0x09, SMBusBase + (SMBHSTDATB + 0x1));
-	outb(0x15, SMBusBase + SMBHSTCNT);
-	//check the status register for busy state
-	//sch_SMbus_regs ();
-	temp = inb(SMBusBase + SMBHSTSTS);
-	//printk(BIOS_DEBUG, "SMBus Busy.. status =%x\r\n",temp);
-	//printk(BIOS_DEBUG, "SMBHSTSTS. =%x\r\n",inb(SMBusBase+SMBHSTSTS));
-	do {
-		temp = inb(SMBusBase + SMBHSTSTS);
-		printk(BIOS_DEBUG, "SMBus Busy.. status =%x\r\n", temp);
-		//sch_SMbus_regs ();
-		printk(BIOS_DEBUG, "SMBHSTSTS. =%x\r\n",
-		       inb(SMBusBase + SMBHSTSTS));
-		if (temp > 0)
-			break;
-	} while (1);
-
-	switch (temp) {
-	case 1:
-		printk(BIOS_DEBUG, "SMBus Success");
-		break;
-	default:
-		printk(BIOS_DEBUG, "SMBus error %d", temp);
-		break;
-
-	}
-	sch_SMbus_regs();
-
-	printk(BIOS_DEBUG, "Command in TRansaction 2=%x\r\n\n",
-	       inb(SMBusBase + SMBHSTCMD));
-}
-
-void transaction3(unsigned char dev_addr)
-{
-	int temp, index, length;
-	u32 SMBusBase;
-
-	SMBusBase = sch_SMbase_read();
-	printk(BIOS_DEBUG, "smb_read_multiple_bytes");
-	smb_clear();
-	data_clear();
-	outb(dev_addr, SMBusBase + SMBHSTADD);
-	outb(0x03, SMBusBase + SMBHSTCMD);
-	outb(0x11, SMBusBase + SMBHSTCNT);
-
-	//data_clear();
-	outb(dev_addr + 1, SMBusBase + SMBHSTADD);
-
-	outb(0x15, SMBusBase + SMBHSTCNT);
-
-	// sch_SMbus_regs ();
-	//check the status register for busy state
-	//temp = inb(SMBusBase+SMBHSTSTS);
-	//printk(BIOS_DEBUG, "SMBus Busy.. status =%x\r\n",temp);
-	//sch_SMbus_regs ();
-	//printk(BIOS_DEBUG, "SMBHSTSTS. =%x\r\n",inb(SMBusBase+SMBHSTSTS));
-	do {
-		temp = inb(SMBusBase + SMBHSTSTS);
-		printk(BIOS_DEBUG, "SMBHSTSTS. =%x\r\n",
-		       inb(SMBusBase + SMBHSTSTS));
-		//sch_SMbus_regs ();
-		if (temp > 0)
-			break;
-	} while (1);
-
-	switch (temp) {
-	case 1:
-		printk(BIOS_DEBUG, "SMBus Success\n");
-		break;
-	default:
-		printk(BIOS_DEBUG, "SMBus error %d", temp);
-		break;
-
-	}
-
-	sch_SMbus_regs();
-	printk(BIOS_DEBUG, "ADDRESS is.. %x\r\n", inb(SMBusBase + SMBHSTADD));
-	length = inb(SMBusBase + SMBHSTDAT0);
-
-	printk(BIOS_DEBUG, "Length is.. %x\r\n", inb(SMBusBase + SMBHSTDAT0));
-
-	printk(BIOS_DEBUG, "Command is... %x\r\n", inb(SMBusBase + SMBHSTDATB));
-	printk(BIOS_DEBUG, "Status .. %x\r\n", inb(SMBusBase + SMBHSTDATB + 1));
-	for (index = 0; index < length; index++)
-		printk(BIOS_DEBUG, "Serial Byte[%x]..%x\r\n", index,
-		       inb(SMBusBase + SMBHSTDATB + index));
-}
-
-int selectcard(void)
-{
-	int i;
-
-	printk(BIOS_DEBUG, "%s", "\r\nCase 9.......\r\n");
-	// send the length byte and command code through RFID interface
-
-	transaction1(RFID_ADDR);
-	transaction2(RFID_ADDR);
-	transaction3(RFID_ADDR);
-	return (1);
-}
-#endif
-
-#include "soc/intel/sch/early_init.c"
-#include <soc/intel/sch/raminit.h>
-#include "soc/intel/sch/raminit.c"
-
-static void sch_enable_lpc(void)
-{
-	/* Initialize the FWH decode/Enable registers according to platform design */
-	pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xD0, 0x00112233);
-	pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xD4, 0xC0000000);
-	pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x60, 0x808A8B8B);
-	pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x64, 0x8F898F89);
-}
-
-static void sch_shadow_CMC(void)
-{
-	u32 reg32;
-
-	/* FIXME: proper dest, proper src, and wbinvd, too */
-	memcpy((void *)CMC_SHADOW, (void *)0xfffd0000, 64 * 1024);
-	// __asm__ volatile ("wbinvd\n"
-	//);
-	printk(BIOS_DEBUG, "copy done ");
-	memcpy((void *)0x3f5f0000, (void *)0x3faf0000, 64 * 1024);
-	printk(BIOS_DEBUG, "copy 2 done ");
-	reg32 = cpuid_eax(0x00000001);
-	printk(BIOS_INFO, "CPU ID: %d.\n", reg32);
-
-	reg32 = cpuid_eax(0x80000008);
-	printk(BIOS_INFO, "Physical Address size: %d.\n", (reg32 & 0xFF));
-	printk(BIOS_INFO, "Virtual Address size: %d.\n",
-	       ((reg32 & 0xFF00) >> 8));
-	sch_port_access_write_ram_cmd(0xB8, 4, 0, 0x3faf0000);
-	printk(BIOS_DEBUG, "1 ");
-	sch_port_access_write_ram_cmd(0xBA, 4, 0, reg32);
-	printk(BIOS_DEBUG, "2 ");
-}
-
-static void poulsbo_setup_Stage1Regs(void)
-{
-	u32 reg32;
-
-	printk(BIOS_DEBUG, "E000/F000 Routing ");
-	reg32 = sch_port_access_read(2, 3, 4);
-	sch_port_access_write(2, 3, 4, (reg32 | 0x6));
-}
-
-static void poulsbo_setup_Stage2Regs(void)
-{
-	u16 reg16;
-
-	printk(BIOS_DEBUG, "Reserved");
-	reg16 = pci_read_config16(PCI_DEV(0, 0x2, 0), 0x62);
-	pci_write_config16(PCI_DEV(0, 0x2, 0), 0x62, (reg16 | 0x3));
-	/* Slot capabilities */
-	pci_write_config32(PCI_DEV(0, 28, 0), 0x54, 0x80500);
-	pci_write_config32(PCI_DEV(0, 28, 1), 0x54, 0x100500);
-	/* FIXME: CPU ID identification */
-	printk(BIOS_DEBUG, " done.\n");
-}
-
-void mainboard_romstage_entry(unsigned long bist)
-{
-	int boot_mode = 0;
-
-	if (bist == 0)
-		enable_lapic();
-
-	sch_enable_lpc();
-	console_init();
-
-	/* Halt if there was a built in self test failure */
-	// report_bist_failure(bist);
-	// outl (0x00, 0x1088);
-
-	/*
-	 * Perform some early chipset initialization required
-	 * before RAM initialization can work.
-	 */
-	sch_early_initialization();
-	sdram_initialize(boot_mode);
-
-	sch_shadow_CMC();
-	poulsbo_setup_Stage1Regs();
-	poulsbo_setup_Stage2Regs();
-#if 0
-	sch_SMbase_init();
-
-	/* Perform some initialization that must run before stage2. */
-#endif
-
-	/*
-	 * This should probably go away. Until now it is required
-	 * and mainboard specific.
-	 */
-
-	/* Chipset Errata! */
-	pci_write_config16(PCI_DEV(0, 0x2, 0), GGC, 0x20);
-	pci_write_config32(PCI_DEV(0, 0x2, 0), 0xc4, 0x00000002);
-	pci_write_config32(PCI_DEV(0, 0x2, 0), 0xe0, 0x00008000);
-	pci_write_config32(PCI_DEV(0, 0x2, 0), 0xf0, 0x00000005);
-	pci_write_config16(PCI_DEV(0, 0x2, 0), 0xf7, 0x80);
-	pci_write_config16(PCI_DEV(0, 0x2, 0), 0x4, 0x7);
-
-#if RFID_TEST
-	sch_SMbase_init();
-	selectcard();
-#endif
-}